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参数资料
| 型号： | A3P030-QNG68II |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 768 CLBS, 30000 GATES, 350 MHz, QCC68 |
| 封装： | 8 X 8 MM, 0.90 MM HEIGHT, 0.40 MM PITCH, GREEN, QFN-68 |
| 文件页数： | 27/49页 |
| 文件大小： | 5893K |
| 代理商： | A3P030-QNG68II |
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ProASIC3 DC and Switching Characteristics
2- 106
v1.3
Advance v0.7
(continued)
In EQ 3-2, 150 was changed to 110 and the result changed from 3.9 to 1.951.
3-5
Table 3-6 Temperature and Voltage Derating Factors for Timing Delays was
updated.
3-6
Table 3-5 Package Thermal Resistivities was updated.
3-5
Table 3-14 Summary of Maximum and Minimum DC Input and Output Levels
Applicable to Commercial and Industrial Conditions—Software Default Settings
(Advanced) and Table 3-17 Summary of Maximum and Minimum DC Input
Levels Applicable to Commercial and Industrial Conditions (Standard Plus) were
updated.
3-17 to
3-17
Table 3-20 Summary of I/O Timing Characteristics—Software Default Settings
(Advanced) and Table 3-21 Summary of I/O Timing Characteristics—Software
Default Settings (Standard Plus) were updated.
3-20 to
3-20
Table
3-11 Different
Components
Contributing
to
Dynamic
Power
Consumption in ProASIC3 Devices was updated.
3-9
Table 3-24 I/O Output Buffer Maximum Resistances1 (Advanced) and Table 3-
25 I/O Output Buffer Maximum Resistances1 (Standard Plus) were updated.
3-22 to
3-22
Table 3-17 Summary of Maximum and Minimum DC Input Levels Applicable to
Commercial and Industrial Conditions was updated.
3-18
Table 3-28 I/O Short Currents IOSH/IOSL (Advanced) and Table 3-29 I/O
Short Currents IOSH/IOSL (Standard Plus) were updated.
3-24 to
3-26
The note in Table 3-32 I/O Input Rise Time, Fall Time, and Related I/O
Reliability was updated.
3-27
Figure 3-33 Write Access After Write onto Same Address, Figure 3-34 Read
Access After Write onto Same Address, and Figure 3-35 Write Access After
Read onto Same Address are new.
3-82 to
3-84
Figure 3-43 Timing Diagram was updated.
3-96
Advance v0.5
(January 2006)
B-LVDS and M-LDVS are new I/O standards added to the datasheet.
N/A
The term flow-through was changed to pass-through.
N/A
Figure 2-7 Efficient Long-Line Resources was updated.
2-7
The footnotes in Figure 2-15 Clock Input Sources Including CLKBUF,
CLKBUF_LVDS/LVPECL, and CLKINT were updated.
2-16
The Delay Increments in the Programmable Delay Blocks specification in Figure
2-24 ProASIC3E CCC Options.
2-24
The "SRAM and FIFO" section was updated.
2-21
The "RESET" section was updated.
2-25
The "WCLK and RCLK" section was updated.
2-25
The "RESET" section was updated.
2-25
The "RESET" section was updated.
2-27
The "Introduction" of the "Advanced I/Os" section was updated.
2-28
Previous Version
Changes in Current Version (v1.3)
Page
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PDF描述 |
|---|---|
| A3P030-VQ100II | FPGA, 768 CLBS, 30000 GATES, 350 MHz, PQFP100 |
| A3P030-VQG100II | FPGA, 768 CLBS, 30000 GATES, 350 MHz, PQFP100 |
| A3P125-1FG144II | FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PBGA144 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| A3P030-VQ100 | 功能描述:IC FPGA 1KB FLASH 30K 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14） |
| A3P030-VQ100I | 功能描述:IC FPGA 1KB FLASH 30K 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14） |
| A3P030-VQ144 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| A3P030-VQ144ES | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| A3P030-VQ144I | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
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