- 您现在的位置：买卖IC网 > PDF目录209983 > A3P125-2VQG100II FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP100 PDF资料下载
参数资料
| 型号： | A3P125-2VQG100II |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP100 |
| 封装： | 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, VQFP-100 |
| 文件页数： | 10/49页 |
| 文件大小： | 5893K |
| 代理商： | A3P125-2VQG100II |
第1页第2页第3页第4页第5页第6页第7页第8页第9页当前第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页
ProASIC3 DC and Switching Characteristics
v1.3
2 - 91
Timing Characteristics
Table 2-107 RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std.
–F
Units
tAS
Address setup time
0.25 0.28 0.33 0.40
ns
tAH
Address hold time
0.00 0.00 0.00 0.00
ns
tENS
REN_B, WEN_B setup time
0.14 0.16 0.19 0.23
ns
tENH
REN_B, WEN_B hold time
0.10 0.11 0.13 0.16
ns
tBKS
BLK_B setup time
0.23 0.27 0.31 0.37
ns
tBKH
BLK_B hold time
0.02 0.02 0.02 0.03
ns
tDS
Input data (DI) setup time
0.18 0.21 0.25 0.29
ns
tDH
Input data (DI) hold time
0.00 0.00 0.00 0.00
ns
tCKQ1
Clock HIGH to new data valid on DO (output retained, WMODE = 0)
2.36 2.68 3.15 3.79
ns
Clock HIGH to new data valid on DO (flow-through, WMODE = 1)
1.79 2.03 2.39 2.87
ns
tCKQ2
Clock HIGH to new data valid on DO (pipelined)
0.89 1.02 1.20 1.44
ns
tWRO
Address collision clk-to-clk delay for reliable read access after write
on same address
TBDTBD TBDTBD
ns
tCCKH
Address collision clk-to-clk delay for reliable write access after
write/read on same address
TBDTBD TBDTBD
ns
tRSTBQ
RESET_B LOW to data out LOW on DO (flow-through)
0.92 1.05 1.23 1.48
ns
RESET_B LOW to Data Out LOW on DO (pipelined)
0.92 1.05 1.23 1.48
ns
tREMRSTB
RESET_B removal
0.29 0.33 0.38 0.46
ns
tRECRSTB
RESET_B recovery
1.50 1.71 2.01 2.41
ns
tMPWRSTB
RESET_B minimum pulse width
0.21 0.24 0.29 0.34
ns
tCYC
Clock cycle time
3.23 3.68 4.32 5.19
ns
FMAX
Maximum frequency
310
272
231
193
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
相关PDF资料 |
PDF描述 |
|---|---|
| A3P125-FG144II | FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PBGA144 |
| A3P125-FGG144II | FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PBGA144 |
| A3P125-PQ208II | FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP208 |
| A3P125-PQG208II | FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP208 |
| A3P125-QN132II | FPGA, 3072 CLBS, 125000 GATES, 350 MHz, BCC132 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A3P125-2VQG144 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| A3P125-2VQG144ES | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| A3P125-2VQG144I | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| A3P125-2VQG144PP | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| A3P125-DIELOT | 制造商:Microsemi Corporation 功能描述:A3P125-DIELOT - Gel-pak, waffle pack, wafer, diced wafer on film |
发布紧急采购，3分钟左右您将得到回复。