参数资料
型号: A3PE1500-FGG484
厂商: Microsemi SoC
文件页数: 152/162页
文件大小: 0K
描述: IC FPGA 1KB FLASH 1.5M 484-FBGA
标准包装: 40
系列: ProASIC3E
RAM 位总计: 276480
输入/输出数: 280
门数: 1500000
电源电压: 1.425 V ~ 1.575 V
安装类型: 表面贴装
工作温度: 0°C ~ 70°C
封装/外壳: 484-BGA
供应商设备封装: 484-FPBGA(23x23)
ProASIC3E Flash Family FPGAs
Revision 13
1-3
Advanced Architecture
The proprietary ProASIC3E architecture provides granularity comparable to standard-cell ASICs. The
ProASIC3E device consists of five distinct and programmable architectural features (Figure 1-1 on
FPGA VersaTiles
Dedicated FlashROM
Dedicated SRAM/FIFO memory
Extensive CCCs and PLLs
Pro I/O structure
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic
function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch
interconnections. The versatility of the ProASIC3E core tile as either a three-input lookup table (LUT)
equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile
capability is unique to the ProASIC family of third-generation architecture Flash FPGAs. VersaTiles are
connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the
device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is
possible for virtually any design.
Figure 1-1 ProASIC3E Device Architecture Overview
4,608-Bit Dual-Port SRAM
or FIFO Block
VersaTile
RAM Block
CCC
Pro I/Os
ISP AES Decryption
User Nonvolatile
FlashROM
Charge Pumps
4,608-Bit Dual-Port SRAM
or FIFO Block
RAM Block
相关PDF资料
PDF描述
M1A3PE1500-FGG484 IC FPGA 1KB FLASH 1.5M 484-FBGA
ASM43DSXS CONN EDGECARD 86POS DIP .156 SLD
ASM43DSEN CONN EDGECARD 86POS .156 EYELET
ASM43DSEH CONN EDGECARD 86POS .156 EYELET
ASM43DRXS CONN EDGECARD 86POS DIP .156 SLD
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