参数资料
型号: A3PN030-Z1QNG48I
元件分类: FPGA
英文描述: FPGA, 768 CLBS, 30000 GATES, QCC48
封装: 6 X 6 MM, 0.90 MM HEIGHT, 0.40 MM PITCH, ROHS COMPLIANT, QFN-48
文件页数: 29/100页
文件大小: 3284K
代理商: A3PN030-Z1QNG48I
ProASIC3 nano DC and Switching Characteristics
2- 20
Advance v0.2
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer.
Table 2-27 Minimum and Maximum DC Input and Output Levels
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH
IOL
IO
H
IOSL
IOSH
IIL
1
IIH
2
Drive Strength
Min.,
V
Max.,
V
Min.,
V
Max.,
V
Max.,
V
Min.,
V
m
A
m
AMax., mA3 Max., mA3
A
4
A
4
2 mA
–0.3
0.8
2
3.6
0.4
2.4
2
25
27
10
4 mA
–0.3
0.8
2
3.6
0.4
2.4
4
25
27
10
6 mA
–0.3
0.8
2
3.6
0.4
2.4
6
51
54
10
8 mA
–0.3
0.8
2
3.6
0.4
2.4
8
51
54
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN <
VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input
current is larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Figure 2-6 AC Loading
Table 2-28 3.3 V LVTTL/LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
CLOAD (pF)
03.3
1.4
10
Notes:
1. Measuring point = Vtrip. See Table 2-16 on page 2-16 for a complete table of trip points.
2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF.
Test Point
Enable Path
Datapath
35 pF
R = 1 k
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
35 pF for tZH/tZHS/tZL/tZLS
5 pF for tHZ/tLZ
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A3PN030-Z1QNG48 FPGA, 768 CLBS, 30000 GATES, QCC48
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