参数资料
型号: A3PN125-1VQ100I
元件分类: FPGA
英文描述: FPGA, 3072 CLBS, 125000 GATES, PQFP100
封装: 14 X 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, VQFP-100
文件页数: 15/106页
文件大小: 3324K
代理商: A3PN125-1VQ100I
ProASIC3 nano DC and Switching Characteristics
2- 2
R e v ision 8
Table 2-2 Recommended Operating Conditions 1, 2
Symbol
Parameter
Extended
Commercial
Industrial
Units
TA
Ambient temperature
–20 to +70 2
–40 to +85 2
°C
TJ
Junction temperature
–20 to +85
–40 to +100
°C
VCC 3
1.5 V DC core supply voltage
1.425 to 1.575
V
VJTAG
JTAG DC voltage
1.4 to 3.6
V
VPUMP 4
Programming voltage
Programming Mode
3.15 to 3.45
V
Operation 4
0 to 3.6
V
VCCPLL 5
Analog power supply (PLL)
1.5 V DC core supply voltage 3
1.425 to 1.575
V
VCCI
and
VMV 7
1.5 V DC supply voltage
1.425 to 1.575
V
1.8 V DC supply voltage
1.7 to 1.9
V
2.5 V DC supply voltage
2.3 to 2.7
V
3.3 V DC supply voltage
3.0 to 3.6
V
3.3 V Wide Range supply voltage 6
2.7 to 3.6
V
Notes:
1. All parameters representing voltages are measured with respect to GND unless otherwise specified.
2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel recommends
that the user follow best design practices using Actel’s timing and power simulation tools.
3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O
standard are given in Table 2-14 on page 2-16. VMV and VCCI should be at the same voltage within a given I/O bank.
4. VPUMP can be left floating during operation (not programming mode).
5. VCCPLL pins should be tied to VCC pins. See the "Pin Descriptions and Packaging" chapter for further information.
6. 3.3 V Wide Range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.
7. VMV pins must be connected to the corresponding VCCI pins. See the "Pin Descriptions and Packaging" chapter for
further information.
Table 2-3 Flash Programming Limits – Retention, Storage and Operating Temperature1
Product
Grade
Programming
Cycles
Program Retention
(biased/unbiased)
Maximum Storage
Temperature TSTG (°C)
2
Maximum Operating
Junction Temperature TJ (°C)
2
Commercial
500
20 years
110
100
Industrial
500
20 years
110
100
Notes:
1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.
2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating
conditions and absolute limits.
相关PDF资料
PDF描述
A3PN125-1VQ100 FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-1VQG100I FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-1VQG100 FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-2VQ100I FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-2VQ100 FPGA, 3072 CLBS, 125000 GATES, PQFP100
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