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参数资料
型号： A40MX04-3VQ80I
元件分类： FPGA
英文描述： FPGA, 547 CLBS, 6000 GATES, 109 MHz, PQFP80
封装： 1 MM HEIGHT, PLASTIC, VQFP-80
文件页数： 75/124页
文件大小： 3142K
代理商： A40MX04-3VQ80I
40MX and 42MX FPGA Families
1- 48
v6.1
Table 32
A42MX09 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Units
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Logic Module Propagation Delays1
tPD1
Single Module
1.2
1.3
1.5
1.8
2.5
ns
tCO
Sequential Clock-to-Q
1.3
1.4
1.6
1.9
2.7
ns
tGO
Latch G-to-Q
1.2
1.4
1.6
1.8
2.6
ns
tRS
Flip-Flop (Latch) Reset-to-Q
1.2
1.6
1.8
2.1
2.9
ns
Logic Module Predicted Routing Delays2
tRD1
FO=1 Routing Delay
0.7
0.8
0.9
1.0
1.4
ns
tRD2
FO=2 Routing Delay
0.9
1.0
1.2
1.4
1.9
ns
tRD3
FO=3 Routing Delay
1.2
1.3
1.5
1.7
2.4
ns
tRD4
FO=4 Routing Delay
1.4
1.5
1.7
2.0
2.9
ns
tRD8
FO=8 Routing Delay
2.3
2.6
2.9
3.4
4.8
ns
Logic Module Sequential Timing3, 4
tSUD
Flip-Flop (Latch) Data Input Set-Up
0.3
0.4
0.5
0.7
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.4
0.5
0.6
0.8
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
3.4
3.8
4.3
5.0
7.0
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
4.5
4.9
5.6
6.6
9.2
ns
tA
Flip-Flop Clock Input Period
3.5
3.8
4.3
5.1
7.1
ns
tINH
Input Buffer Latch Hold
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.3
0.4
0.6
ns
tOUTH
Output Buffer Latch Hold
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.3
0.4
0.6
ns
fMAX
Flip-Flop (Latch) Clock Frequency
268
244
224
195
117
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相关PDF资料
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相关代理商/技术参数
参数描述
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A40MX04-3VQG80 功能描述:IC FPGA MX SGL CHIP 6K 80-VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:90 系列:ProASIC3 LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:36864 输入/输出数:157 门数:250000 电源电压:1.425 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 125°C 封装/外壳:256-LBGA 供应商设备封装:256-FPBGA（17x17）
A40MX04-3VQG80I 功能描述:IC FPGA MX SGL CHIP 6K 80-VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27）
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A40MX04-BG100ES 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:40MX and 42MX FPGA Families
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