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参数资料
型号： A40MX04-PL44MX79
元件分类： FPGA
英文描述： FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC44
封装： PLASTIC, LCC-44
文件页数： 35/124页
文件大小： 3142K
代理商： A40MX04-PL44MX79
40MX and 42MX FPGA Families
1- 12
v6.1
JTAG Mode Activation
The JTAG test logic circuit is activated in the Designer
software by selecting Tools -> Device Selection. This
brings up the Device Selection dialog box as shown in
Figure 1-15. The JTAG test logic circuit can be enabled by
clicking the "Reserve JTAG Pins" check box. Table 5
explains the pins' behavior in either mode.
TRST Pin and TAP Controller Reset
An active reset (TRST) pin is not supported; however, MX
devices contain power-on circuitry that resets the
boundary scan circuitry upon power-up. Also, the TMS
pin is equipped with an internal pull-up resistor. This
allows the TAP controller to remain in or return to the
Test-Logic-Reset state when there is no input or when a
logical 1 is on the TMS pin. To reset the controller, TMS
must be HIGH for at least five TCK cycles.
Boundary Scan Description Language
(BSDL) File
Conforming to the IEEE Standard 1149.1 requires that
the operation of the various JTAG components be
documented. The BSDL file provides the standard format
to describe the JTAG components that can be used by
automatic test equipment software. The file includes the
instructions that are supported, instruction bit pattern,
and the boundary-scan chain order. For an in-depth
discussion on BSDL files, please refer to Actel BSDL Files
Format Description application note.
Actel BSDL files are grouped into two categories -
generic and device-specific. The generic files assign all
user I/Os as inouts. Device-specific files assign user I/Os as
inputs, outputs or inouts.
Generic files for MX devices are available on Actel's website
at http://www.actel.com/techdocs/models/bsdl.html.
Figure 1-15 Device Selection Wizard
Table 5
Boundary Scan Pin Configuration and Functionality
Reserve JTAG
Checked
Unchecked
TCK
BST input; must be terminated to logical HIGH or LOW to avoid floating
User I/O
TDI, TMS
BST input; may float or be tied to HIGH
User I/O
TDO
BST output; may float or be connected to TDI of another device
User I/O
相关PDF资料
PDF描述
A40MX04-PL44M FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC44
A40MX04-PL44X79 FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC44
A40MX04-PL44 FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC44
A40MX04-PL68IX79 FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC68
A40MX04-PL68I FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC68
相关代理商/技术参数
参数描述
A40MX04-PL68 功能描述:IC FPGA MX SGL CHIP 6K 68-PLCC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:90 系列:ProASIC3 LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:36864 输入/输出数:157 门数:250000 电源电压:1.425 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 125°C 封装/外壳:256-LBGA 供应商设备封装:256-FPBGA（17x17）
A40MX04-PL68I 功能描述:IC FPGA MX SGL CHIP 6K 68-PLCC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:90 系列:ProASIC3 LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:36864 输入/输出数:157 门数:250000 电源电压:1.425 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 125°C 封装/外壳:256-LBGA 供应商设备封装:256-FPBGA（17x17）
A40MX04-PL68M 制造商:Microsemi Corporation 功能描述:FPGA 40MX Family 6K Gates 547 Cells 83MHz/139MHz 0.45um Technology 3.3V/5V 68-Pin PLCC 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 68PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC FPGA 57 I/O 68PLCC 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 6K 68-PLCC
A40MX04-PL68X4 制造商:Microsemi Corporation 功能描述:MX SERIES 6000 GATES FPGA
A40MX04-PL84 功能描述:IC FPGA MX SGL CHIP 6K 84-PLCC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:90 系列:ProASIC3 LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:36864 输入/输出数:157 门数:250000 电源电压:1.425 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 125°C 封装/外壳:256-LBGA 供应商设备封装:256-FPBGA（17x17）
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