参数资料
型号: A42MX09-FVQ100
厂商: Microsemi SoC
文件页数: 91/142页
文件大小: 0K
描述: IC FPGA MX SGL CHIP 14K 100-VQFP
标准包装: 90
系列: MX
输入/输出数: 83
门数: 14000
电源电压: 3 V ~ 3.6 V,4.75 V ~ 5.25 V
安装类型: 表面贴装
工作温度: 0°C ~ 70°C
封装/外壳: 100-TQFP
供应商设备封装: 100-VQFP(14x14)
40MX and 42MX FPGA Families
1- 48
R e v i sio n 1 1
CMOS Output Module Timing1
tDLH
Data-to-Pad HIGH
3.9
4.5
5.1
6.05
8.5
ns
tDHL
Data-to-Pad LOW
3.4
3.9
4.4
5.2
7.3
ns
tENZH
Enable Pad Z to HIGH
3.4
3.9
4.4
5.2
7.3
ns
tENZL
Enable Pad Z to LOW
4.9
5.6
6.4
7.5
10.5
ns
tENHZ
Enable Pad HIGH to Z
7.9
9.1
10.4
12.2
17.0
ns
tENLZ
Enable Pad LOW to Z
5.9
6.8
7.7
9.0
12.6
ns
dTLH
Delta LOW to HIGH
0.03
0.04
0.05
0.07
ns/pF
dTHL
Delta HIGH to LOW
0.02
0.03
0.04
ns/pF
Table 1-30 A40MX04 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
–3 Speed
–2 Speed
–1 Speed
Std Speed
–F Speed
Units
Parameter / Description
Min. Max.
Min.
Max. Min. Max. Min. Max. Min. Max.
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to
check the hold time for this macro.
4. Delays based on 35 pF loading.
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A42MX09-FVQ100A 制造商:未知厂家 制造商全称:未知厂家 功能描述:40MX and 42MX FPGA Families
A42MX09-FVQ100B 制造商:未知厂家 制造商全称:未知厂家 功能描述:40MX and 42MX FPGA Families
A42MX09-FVQ100ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:40MX and 42MX FPGA Families
A42MX09-FVQ100I 制造商:未知厂家 制造商全称:未知厂家 功能描述:40MX and 42MX FPGA Families
A42MX09-FVQ100M 制造商:未知厂家 制造商全称:未知厂家 功能描述:40MX and 42MX FPGA Families