参数资料
型号: A42MX09-TQG176
厂商: Microsemi SoC
文件页数: 113/142页
文件大小: 0K
描述: IC FPGA 104I/O 176TQFP
标准包装: 40
系列: MX
输入/输出数: 104
门数: 14000
电源电压: 3 V ~ 3.6 V,4.75 V ~ 5.25 V
安装类型: 表面贴装
工作温度: 0°C ~ 70°C
封装/外壳: 176-LQFP
供应商设备封装: 176-TQFP(24x24)
其它名称: 1100-1051
40MX and 42MX FPGA Families
1- 68
R e v i sio n 1 1
Input Module Predicted Routing Delays2
tIRD1
FO = 1 Routing Delay
1.8
2.0
2.3
2.7
3.8
ns
tIRD2
FO = 2 Routing Delay
2.1
2.3
2.6
3.1
4.3
ns
tIRD3
FO = 3 Routing Delay
2.3
2.5
2.9
3.4
4.8
ns
tIRD4
FO = 4 Routing Delay
2.5
2.8
3.2
3.7
5.2
ns
tIRD8
FO = 8 Routing Delay
3.4
3.8
4.3
5.1
7.1
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 486
2.6
2.9
3.2
3.3
3.6
3.9
4.3
5.4
5.9
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 486
3.7
4.3
4.1
4.7
4.6
5.4
6.3
7.6
8.8
ns
tPWH
Minimum Pulse
Width HIGH
FO = 32
FO = 486
2.2
2.4
2.6
2.7
3.0
3.2
3.5
4.5
4.9
ns
tPWL
Minimum Pulse
Width LOW
FO = 32
FO = 486
2.2
2.4
2.6
2.7
3.0
3.2
3.5
4.5
4.9
ns
tCKSW
Maximum Skew
FO = 32
FO = 486
0.5
0.6
0.7
0.8
1.1
ns
tSUEXT
Input Latch External
Set-Up
FO = 32
FO = 486
0.0
ns
tHEXT
Input Latch External
Hold
FO = 32
FO = 486
2.8
3.3
3.1
3.7
3.5
4.2
4.1
4.9
5.7
6.9
ns
tP
Minimum Period
(1/fMAX)
FO = 32
FO = 486
4.7
5.1
5.2
5.7
6.2
6.5
7.1
10.9
11.9
ns
Table 1-36 A42MX24 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed
–2 Speed
–1 Speed
Std Speed
–F Speed
Parameter / Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
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