参数资料
| 型号： | A42MX16-1PLG84 |
| 厂商： | Microsemi SoC |
| 文件页数： | 130/142页 |
| 文件大小： | 0K |
| 描述： | IC FPGA MX SGL CHIP 24K 84-PLCC |
| 标准包装： | 16 |
| 系列： | MX |
| 输入/输出数： | 72 |
| 门数： | 24000 |
| 电源电压： | 3 V ~ 3.6 V，4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 84-LCC（J 形引线） |
| 供应商设备封装： | 84-PLCC（29.31x29.31） |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页当前第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页
40MX and 42MX FPGA Families
1- 84
R e v i sio n 1 1
SDI, I/O
Serial Data Input
Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is LOW.
SDO, I/O
Serial Data Output
Serial data output for diagnostic probe and device programming. SDO is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is LOW. SDO is available for 42MX devices only.
When Silicon Explorer II is being used, SDO will act as an output while the "checksum" command is run.
It will return to user I/O when "checksum" is complete.
TCK, I/O
Test Clock
Clock signal to shift the Boundary Scan Test (BST) data into the device. This pin functions as an I/O
when "Reserve JTAG" is not checked in the Designer Software. BST pins are only available in A42MX24
and A42MX36 devices.
TDI, I/O
Test Data In
Serial data input for BST instructions and data. Data is shifted in on the rising edge of TCK. This pin
functions as an I/O when "Reserve JTAG" is not checked in the Designer Software. BST pins are only
available in A42MX24 and A42MX36 devices.
TDO, I/O
Test Data Out
Serial data output for BST instructions and test data. This pin functions as an I/O when "Reserve JTAG"
is not checked in the Designer Software. BST pins are only available in A42MX24 and A42MX36
devices.
TMS, I/O
Test Mode Select
The TMS pin controls the use of the IEEE 1149.1 Boundary Scan pins (TCK, TDI, TDO). In flexible mode
when the TMS pin is set LOW, the TCK, TDI and TDO pins are boundary scan pins. Once the boundary
scan pins are in test mode, they will remain in that mode until the internal boundary scan state machine
reaches the "logic reset" state. At this point, the boundary scan pins will be released and will function as
regular I/O pins. The "logic reset" state is reached 5 TCK cycles after the TMS pin is set HIGH. In
dedicated test mode, TMS functions as specified in the IEEE 1149.1 specifications. IEEE JTAG
specification recommends a 10k
Ω pull-up resistor on the pin. BST pins are only available in A42MX24
and A42MX36 devices.
VCC
Supply Voltage
Input supply voltage for 40MX devices
VCCA
Supply Voltage
Supply voltage for array in 42MX devices
VCCI
Supply Voltage
Supply voltage for I/Os in 42MX devices
WD, I/O
Wide Decode Output
When a wide decode module is used in a 42MX device this pin can be used as a dedicated output from
the wide decode module. This direct connection eliminates additional interconnect delays associated
with regular logic modules. To implement the direct I/O connection, connect an output buffer of any type
to the output of the wide decode macro and place this output on one of the reserved WD pins.
相关PDF资料 |
PDF描述 |
|---|---|
| A42MX09-2PQG100 | IC FPGA MX SGL CHIP 14K 100-PQFP |
| A42MX09-2PQ100 | IC FPGA MX SGL CHIP 14K 100-PQFP |
| ACM44DRTI-S13 | CONN EDGECARD EXTEND 88POS 0.156 |
| ABM44DRTI-S13 | CONN EDGECARD EXTEND 88POS .156 |
| RCB80DHBS | CONN EDGECARD 160PS R/A .050 DIP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A42MX16-1PLG84I | 功能描述:IC FPGA MX SGL CHIP 24K 84-PLCC RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX16-1PLG84M | 制造商:Microsemi Corporation 功能描述:FPGA 24K GATES 608 CELLS 119MHZ/198MHZ 0.45UM 3.3V/5V 84PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC FPGA 72 I/O 84PLCC 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 24K 84-PLCC |
| A42MX16-1PQ100 | 功能描述:IC FPGA MX SGL CHIP 24K 100-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX16-1PQ100A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1PQ100B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:40MX and 42MX FPGA Families |
发布紧急采购，3分钟左右您将得到回复。