参数资料
型号: A4401KL-T
厂商: Allegro Microsystems Inc
文件页数: 9/17页
文件大小: 0K
描述: IC QUASI FLYBACK CONVERTER 8SOIC
标准包装: 98
显示器类型: 真空荧光 (VF)
电流 - 电源: 2.3mA
电源电压: 7 V ~ 40 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 管件
A4401
Automotive Quasi-Resonant Flyback Control IC
I RMS = 4 × I LOAD × ? ?
? 3 ?
1
(17)
for more information).The current that flows in and
out of the capacitor is similar to the current that flows
through the corresponding rectifier diode.
Worst case power dissipation due to the ESR will
occur at V BAT (min) and maximum load. The duty
cycle under these conditions is a maximum of 0.7.
The rms current in the capacitor can be found as fol-
lows:
? 0.7 ? ?
.
(16)
When selecting a suitable capacitor, the rms current
rating should have reasonable margin with respect to
the above value. In addition, the current rating should
be derated to take into account the frequency correc-
tion at values of less than 100 kHz.
The impedance of the output capacitor will affect the
amount of voltage ripple and noise that appears on
the output. The impedance is composed of two com-
ponents: ESR and reactance, X C . Even with a modest
amount of capacitance on the output, the ESR will
tend to dominate the overall impedance.
The ESR can be estimated by multiplying the capaci-
tance reactance by the dissipation factor, DF (tan δ ):
ESR = × DF .
2× × f SW × C OUT
power stage effectively contains one pole formed by
the output capacitors and loads.
In terms of “closing the loop,” the optimal shaping
components are shown in the Functional Block dia-
gram, connected to the COMP pin. The control loop is
optimized for an equivalent output capacitor of 22 μ F.
Larger capacitor values can be used, however, those
will tend to reduce the bandwidth of the control loop.
Smaller values should not be used, as they may cause
instability issues.
Magnetics Design
The following are the known variables:
? Maximum output power, P OUT .
? Minimum battery voltage, V BAT (min).
? Minimum switching frequency, f SW (min). This
occurs at V BAT (min) and maximum load. Note, it
is recommended that the lowest possible switching
frequency be used, in order to minimize switching
losses and to shift the differential harmonics down
the frequency spectrum. This is a compromise with
the sizing of the magnetics and filtering components.
? Maximum duty cycle. This should typically not
exceed 0.7, in order to avoid excessive losses in the
secondary output circuits.
V pk-pk = ESR × I LOAD × 4
Note that DF is normally quoted at 25°C, however,
it is usually fairly constant as the temperature is
increased.
The peak to peak voltage can then be found:
.
(18)
? Efficiency of converter, η % , at V BAT (min). This will
typically be between 80% and 85%.
? Resonant capacitor, C11, connected between the
LX pin and ground. The resonant half period of 1 μ s
may be achieved with the parasitic capacitance that
The voltage rating should be chosen to provide at least
a 20% margin above the maximum output voltage.
Control Loop
As the converter operates in discontinuous mode,
the inductor does not feature in the power stage. The
exists in the circuit. Fine tuning can be performed by
adding additional capacitance.
? Known magnetic core set. Material selection should
be based on performance at elevated temperature,
and include consideration of flux density, losses,
Curie temperature, and so forth.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
9
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