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| 型号： | A4491EESTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 6/16页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2.2A TRPL 20QFN |
| 标准包装： | 9,000 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 3 |
| 输出电压： | 可调至 0.8V |
| 输入电压： | 4.5 V ~ 23 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 550kHz |
| 电流 - 输出： | 2.2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 20-QFN（4x4） |
A4491
Triple Output Step-Down Switching Regulator
Functional Description
Basic Operation
The A4491 contains three fixed frequency, buck switching con-
verters with peak current-mode control, including slope compen-
sation. Each converter can be independently turned on and off via
the enable inputs (EN1, EN2, and EN3), which are active high.
When enabled, the corresponding output is brought-up under the
control of a soft start routine, which avoids output voltage over-
shoot and minimizes input inrush current.
The output voltage is typically divided down by an external
potential divider, and is compared against an internal reference
voltage to produce an error signal, also known as the current
demand signal . The current signal through the buck switch is
converted into a voltage. This signal is then compared against the
current demand signal to create the required duty cycle.
At the beginning of each switching cycle, the buck switch is
turned on. When the current signal through the switch reaches the
level of the current demand signal, the on-time of the switch is
terminated. On the next switching cycle, the switch is turned on
again and the cycle is repeated.
One shared clock is used to define the switching frequency for
each regulator. Each of the three switching cycles (REG1, REG2,
and REG3) are phase shifted with respect to one another by 120°
in an attempt to minimize the pulsed current drawn from the
input filter capacitors. Under certain conditions, for example at
low V BB conditions and relatively high user-set output voltages,
switching overlap between channels is inevitable.
Under conditions, such as light loads or high V BB voltages, that
cause duty cycles (DC) of less than the minimum value, the
converter enters a pulse-skipping mode to ensure regulation is
maintained.
A charge pump regulator is provided to ensure a sufficient gate
drive is available for all three power switches across the full input
voltage range. This regulator allows operation even at very wide
operating duty cycles. On initial power-up, an internal regulator
is used to provide the bias supply for on-chip control functions.
Each regulator channel utilizes pulse-by-pulse current limiting in
the event of either a short circuit or an overload. If the overload
is applied long enough, the IC temperature may rise sufficiently
to cause the thermal shutdown circuit to operate. The part will
auto-restart under control of the soft start circuit after the thermal
disable condition is removed, and assuming all other conditions
are met. See the Shutdown section for more information.
Power Configuration
The A4491 supports alternative schemes for providing logic sup-
ply voltage on the VDD pin. In addition, the IC can be powered
up and down using either the VBB or ENB pins.
Powering VDD To minimize power dissipation, especially at
high input voltages, it is recommended that an external sup-
ply be applied to the VDD input pin. Typically, this voltage is
derived from one of the three regulated outputs that are set-up for
between 3.3 and 5 V (V REGx ).
Another advantage of powering the VDD externally is that the
VBB undervoltage lockout level is lowered. To maximize the
run time of the switchers during a VBB power-down condition,
two alternative undervoltage shutdown conditions are supported,
depending on which VDD-powering configuration has been
implemented. When no external VDD is applied, the minimum
V BB , V BBUV(sd) , is 4.1 V typical. When an external VDD is
applied, the minimum V BB , V BBCPUV(sd) , is 3.5 V typical.
One note of caution when deriving VDD from a VREG output:
during initial application of V BB , the internal bias supply auto-
matically starts from the internal regulator because VREG has not
yet reached regulation. This means the startup threshold is deter-
mined by V BBUV(su) (4.3 V typical) because there is no external
VDD. When VREG has begun to supply VDD externally, the
shutdown threshold reduces to V BBCPUV(sd) (3.5 V typical). This
assumes that V REG is present.
Powering Up and Down with VBB Referring to figure 1,
each of the enable inputs (ENBx) are held high by being tied to
the V BB rail via a 100 k Ω resistor and the VDD is supplied from
one of the regulator outputs. When the V BB voltage reaches the
minimum threshold, V BBUV(su) , the charge pump supply (VCP)
ramps up. When V BB + V CP has reached the minimum thresh-
old V BBCPUV(su) , the soft start routines are initiated (t SS ) for all
three regulator channels (VREGx). When all three regulators
have reached the 85% FBx threshold, the power-on-reset timer
is initiated. After the power-on-reset period, t POR , has elapsed,
PORZ goes high, indicating that all the regulators and V BB are in
specification.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
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相关代理商/技术参数 |
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| A4492 | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:Designed to provide the power supply requirements for automotive applications, the A4492 provides three high current, high performance, switching regulator outputs with independent soft start. |
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