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| 型号： | A4931METTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 4/9页 |
| 文件大小： | 0K |
| 描述： | IC DC MOTOR PREDRIVER 3PH 28QFN |
| 标准包装： | 1 |
| 应用： | DC 电机驱动器，无刷（BLDC），3 相 |
| 输出数： | 1 |
| 电源电压： | 8 V ~ 33 V |
| 工作温度： | -20°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VFQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN/MLP 裸露焊盘（5x5） |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1214-6 |
A4931
3-Phase Brushless DC Motor Pre-Driver
ELECTRICAL CHARACTERISTICS * Valid at T A = 25°C, V BB = 24 V, unless noted otherwise
Characteristics
Supply Voltage Range
Motor Supply Current
HBIAS
HBIAS Current Limit
Symbol
V BB
I BB
V HBIAS
I HBIASlim
Test Conditions
Operating
f PWM < 30 kHz, C LOAD = 1000 pF
Charge pump on, outputs disabled, Standby mode
0 mA ≤ I HBIAS ≤ 24 mA
Min.
8
–
–
7.2
30
Typ.
–
5
3
7.5
–
Max.
V BBOV
6
3.5
7.8
–
Units
V
mA
mA
V
mA
Control Logic
Logic Input Voltage
V IN(1)
V IN(0)
2
–
–
–
–
0.8
V
V
Logic Input Current
Input Pin Glitch Reject
ENB Standby Pulse Propagation Delay
HBIAS Wake-up Delay, Standby Mode
I IN(1)
I IN(0)
t GLITCH
t dENB
t dHBIAS
V IN = 2 V
V IN = 0.8 V
ENB pin
DIR, BRAKEZ pins
To outputs off
C HBIAS = 0.1 μ F
–1
–1
350
700
2.1
–
<1.0
<–1.0
500
1000
3
15
1
1
650
1300
3.9
25
μ A
μ A
ns
ns
ms
μ s
Gate Drive
High-Side Gate Drive Output
Low-Side Gate Drive Output
Gate Drive Current (Sourcing)
Gate Drive Pull Down Resistance
Dead Time
Current Limit Input Threshold
Fixed Off-Time
V GS(H)
V GS(L)
I Gate
R Gate
t dead
V REF
t OFF
Relative to V BB , I GATE = 2 mA
I GATE = 2 mA
GH = GL = 4 V
7
7
20
10
700
180
18
–
–
30
28
1000
200
25
–
–
–
40
1300
220
37
V
V
mA
Ω
ns
mV
μ s
Protection
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
T JTSD
T JTSDhys
155
14
170
15
185
26
°C
°C
VBB UVLO Enable Threshold
VBB UVLO Hysteresis
VCP UVLO
Lock Detect Duration
VBB Overvoltage Threshold
V BBUV
V BBUVhys
V CPUV
t lock
V BBOV
Rising V BB
Relative to V BB
C = 0.1 μ F
Rising V BB
6.2
0.4
4.6
1.5
30
7
0.75
–
2
33
7.85
1
6
2.5
37.5
V
V
V
s
V
Hall Logic
Hall Input Current
Common Mode Input Range
AC Input Voltage Range
Hall Thresholds
Hall Threshold Hysteresis
Pulse Reject Filter
I HALL
V CMR
V HALL
V th
V HYS
t pulse
V IN = 0.2 to 3.5 V
Difference between Hall inputs at transitions
T J = 25°C
T J = –20°C to 125°C
–1
0.2
60
–
10
5
–
0
–
–
+10,–10
20
20
2
1
3.5
–
–
30
40
–
μ A
V
mV p-p
mV
mV
mV
μ s
FG
FG Output Saturation Voltage
FG Leakage Current
V FG(sat)
I FGlkg
I FG = 2 mA
V FG = 5 V
–
–
–
–
0.5
1
V
μ A
*Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
Specifications throughout the allowed operating temperature range are guaranteed by design and characterization.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
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