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| 型号： | A4935KJP-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 21/25页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DRIVER 3PH AUTO 48LQFP |
| 标准包装： | 250 |
| 配置： | 3 相桥 |
| 输入类型： | PWM |
| 延迟时间： | 90ns |
| 配置数： | 1 |
| 输出数： | 3 |
| 电源电压： | 5.5 V ~ 50 V |
| 工作温度： | -40°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP 裸露焊盘 |
| 供应商设备封装： | 48-LQFP 裸露焊盘（7x7） |
| 包装： | 托盘 |
A4935
Automotive 3-Phase MOSFET Driver
? Sensitive connections such as RDEAD and VDSTH, which
have very little ground current, should be connected to the Quiet
ground (refer to figure 5), which is connected independently,
closest to the AGND pin. These sensitive components should
never be connected directly to the supply common or to a
common ground plane. They must be referenced directly to the
AGND pin.
? The supply decoupling for VBB, VREG, and VDD should be
connected to the Controller Supply ground, which is connected
independently, close to the PGND pin. The decoupling
capacitors should also be connected as close as practicable to
the relevant supply pin.
? If layout space is limited, then the Quiet ground and the
Controller Supply ground may be combined. In this case, ensure
that the ground return of the dead time resistor is close to the
AGND pin.
? Check the peak voltage excursion of the transients on the LSS
pin with reference to the AGND pin, using a close grounded (tip
and barrel) probe. If the voltage at LSS exceeds the absolute
maximum shown in this datasheet, add additional clamping and
capacitance between the LSS pin and the AGND pin as shown
in figure 5.
? Gate charge drive paths and gate discharge return paths may
carry a large transient current pulse. Therefore, the traces from
GHx, GLx, Sx, and LSS should be as short as possible to reduce
the circuit trace inductance.
? Provide an independent connection from LSS to the common
point of the power bridge. It is not recommended to connect
LSS directly to an xGND pin, as this may inject noise into
sensitive functions such as the timer for dead time. The LSS
connection should not be used for the CSP connection.
? The inputs to the sense amplifier, CSP and CSN, should have
independent circuit traces. For best results, they should be
matched in length and route.
? A low-cost diode can be placed in the connection to VBB to
provide reverse battery protection. In reverse battery conditions,
it is possible to use the body diodes of the power FETs to clamp
the reverse voltage to approximately 4 V. In this case, the
additional diode in the VBB connection will prevent damage
to the A4935 and the VDRAIN input will survive the
reverse voltage.
Note that the above are only recommendations. Each application
is different and may encounter different sensitivities. A driver
running a few amps will be less susceptible than one running with
150 A, and each design should be tested at the maximum current
to ensure any parasitic effects are eliminated.
Optional reverse
battery protection
VREG
VBB VDRAIN
GHC
GHB
GHA
A4935
+ Supply
VDD
VDSTH
RDEAD
AGND
SA
SB
SC
GLA
GLB
GLC
LSS
PGND
R S
Motor
Quiet Ground
Optional components
to limit LSS transients
Power Ground
Supply
Common
Controller Supply Ground
Figure 5. Supply routing suggestions
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
21
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