参数资料
| 型号： | A54SX08-1VQ100 |
| 厂商： | Microsemi SoC |
| 文件页数： | 45/64页 |
| 文件大小： | 0K |
| 描述： | IC FPGA SX 12K GATES 100-VQFP |
| 标准包装： | 90 |
| 系列： | SX |
| LAB/CLB数： | 768 |
| 输入/输出数： | 81 |
| 门数： | 12000 |
| 电源电压： | 3 V ~ 3.6 V，4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 100-TQFP |
| 供应商设备封装： | 100-VQFP（14x14） |
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SX Family FPGAs
v3.2
1-1
SX Family FPGAs
General Description
The Actel SX family of FPGAs features a sea-of-modules
architecture that delivers device performance and
integration levels not currently achieved by any other
FPGA architecture. SX devices greatly simplify design
time, enable dramatic reductions in design costs and
power consumption, and further decrease time to
market for performance-intensive applications.
The Actel SX architecture features two types of logic
modules, the combinatorial cell (C-cell) and the register
cell (R-cell), each optimized for fast and efficient
mapping of synthesized logic functions. The routing and
interconnect resources are in the metal layers above the
logic modules, providing optimal use of silicon. This
enables the entire floor of the device to be spanned with
an uninterrupted grid of fine-grained, synthesis-friendly
logic modules (or “sea-of-modules”), which reduces the
distance signals have to travel between logic modules. To
minimize signal propagation delay, SX devices employ
both local and general routing resources. The high-speed
local routing resources (DirectConnect and FastConnect)
enable very fast local signal propagation that is optimal
for fast counters, state machines, and datapath logic.
The general system of segmented routing tracks allows
any logic module in the array to be connected to any
other
logic
or
I/O
module.
Within
this
system,
propagation delay is minimized by limiting the number
of antifuse interconnect elements to five (90 percent of
connections typically use only three antifuses). The
unique local and general routing structure featured in
SX devices gives fast and predictable performance,
allows 100 percent pin-locking with full logic utilization,
enables concurrent PCB development, reduces design
time, and allows designers to achieve performance goals
with minimum effort.
Further complementing SX’s flexible routing structure is
a hardwired, constantly loaded clock network that has
been tuned to provide fast clock propagation with
minimal clock skew. Additionally, the high performance
of the internal logic has eliminated the need to embed
latches or flip-flops in the I/O cells to achieve fast clock-
to-out or fast input setup times. SX devices have easy to
use I/O cells that do not require HDL instantiation,
facilitating design reuse and reducing design and
verification time.
SX Family Architecture
The SX family architecture was designed to satisfy next-
generation performance and integration requirements
for production-volume designs in a broad range of
applications.
Programmable Interconnect Element
The SX family provides efficient use of silicon by locating
the routing interconnect resources between the Metal 2
(M2) and Metal 3 (M3) layers (Figure 1-1 on page 1-2).
This completely eliminates the channels of routing and
interconnect resources between logic modules (as
implemented on SRAM FPGAs and previous generations
of antifuse FPGAs), and enables the entire floor of the
device to be spanned with an uninterrupted grid of logic
modules.
Interconnection between these logic modules is achieved
using The Actel patented metal-to-metal programmable
antifuse interconnect elements, which are embedded
between the M2 and M3 layers. The antifuses are
normally open circuit and, when programmed, form a
permanent low-impedance connection.
The extremely small size of these interconnect elements
gives the SX family abundant routing resources and
provides excellent protection against design pirating.
Reverse engineering is virtually impossible because it is
extremely difficult to distinguish between programmed
and
unprogrammed
antifuses,
and
there
is
no
configuration bitstream to intercept.
Additionally,
the
interconnect
elements
(i.e.,
the
antifuses and metal tracks) have lower capacitance and
lower resistance than any other device of similar
capacity, leading to the fastest signal propagation in the
industry.
Logic Module Design
The SX family architecture is described as a “sea-of-
modules” architecture because the entire floor of the
device is covered with a grid of logic modules with
virtually no chip area lost to interconnect elements or
routing. The Actel SX family provides two types of logic
modules, the register cell (R-cell) and the combinatorial
cell (C-cell).
相关PDF资料 |
PDF描述 |
|---|---|
| A54SX08-1VQG100 | IC FPGA SX 12K GATES 100-VQFP |
| A42MX16-PQG208 | IC FPGA MX SGL CHIP 24K 208-PQFP |
| A42MX16-PQ208 | IC FPGA MX SGL CHIP 24K 208-PQFP |
| A42MX09-3PQ100 | IC FPGA MX SGL CHIP 14K 100-PQFP |
| EMC55DRSN-S273 | CONN EDGECARD 110PS DIP .100 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A54SX08-1VQ100I | 功能描述:IC FPGA SX 12K GATES 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:SX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A54SX08-1VQ100M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| A54SX08-1VQ208 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:54SX Family FPGAs |
| A54SX08-1VQ208I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:54SX Family FPGAs |
| A54SX08-1VQ208M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:54SX Family FPGAs |
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