参数资料
| 型号： | A54SX08A-FPQ208 |
| 厂商： | Microsemi SoC |
| 文件页数： | 14/108页 |
| 文件大小： | 0K |
| 描述： | IC FPGA SX 12K GATES 208-PQFP |
| 标准包装： | 24 |
| 系列： | SX-A |
| LAB/CLB数： | 768 |
| 输入/输出数： | 130 |
| 门数： | 12000 |
| 电源电压： | 2.25 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 208-BFQFP |
| 供应商设备封装： | 208-PQFP（28x28） |
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SX-A Family FPGAs
v5.3
1-9
Boundary-Scan Testing (BST)
All SX-A devices are IEEE 1149.1 compliant and offer
superior diagnostic and testing capabilities by providing
Boundary Scan Testing (BST) and probing capabilities.
The BST function is controlled through the special JTAG
pins (TMS, TDI, TCK, TDO, and TRST). The functionality of
the JTAG pins is defined by two available modes:
Dedicated and Flexible. TMS cannot be employed as a
user I/O in either mode.
Dedicated Mode
In Dedicated mode, all JTAG pins are reserved for BST;
designers cannot use them as regular I/Os. An internal
pull-up resistor is automatically enabled on both TMS
and TDI pins, and the TMS pin will function as defined in
the IEEE 1149.1 (JTAG) specification.
To select Dedicated mode, the user must reserve the
JTAG pins in Actel’s Designer software. Reserve the JTAG
pins by checking the Reserve JTAG box in the Device
Selection Wizard (Figure 1-12).
The default for the software is Flexible mode; all boxes
are unchecked. Table 1-5 lists the definitions of the
options in the Device Selection Wizard.
Flexible Mode
In Flexible mode, TDI, TCK, and TDO may be employed as
either user I/Os or as JTAG input pins. The internal
resistors on the TMS and TDI pins are not present in
flexible JTAG mode.
To select the Flexible mode, uncheck the Reserve JTAG
box in the Device Selection Wizard dialog in the Actel
Designer software. In Flexible mode, TDI, TCK, and TDO
pins may function as user I/Os or BST pins. The
functionality is controlled by the BST Test Access Port
(TAP) controller. The TAP controller receives two control
inputs, TMS and TCK. Upon power-up, the TAP controller
enters the Test-Logic-Reset state. In this state, TDI, TCK,
and TDO function as user I/Os. The TDI, TCK, and TDO are
transformed from user I/Os into BST pins when a rising
edge on TCK is detected while TMS is at logic low. To
return to Test-Logic Reset state, TMS must be high for at
least five TCK cycles. An external 10 k pull-up resistor
to VCCI should be placed on the TMS pin to pull it
High by default.
describes
the
different
configuration
requirements of BST pins and their functionality in
different modes.
TRST Pin
The TRST pin functions as a dedicated Boundary-Scan
Reset pin when the Reserve JTAG Test Reset option is
selected as shown in Figure 1-12. An internal pull-up
resistor is permanently enabled on the TRST pin in this
mode. Actel recommends connecting this pin to ground
in normal operation to keep the JTAG state controller in
the Test-Logic-Reset state. When JTAG is being used, it
can be left floating or can be driven high.
When the Reserve JTAG Test Reset option is not
selected, this pin will function as a regular I/O. If unused
as an I/O in the design, it will be configured as a tristated
output.
Figure 1-12 Device Selection Wizard
Table 1-5 Reserve Pin Definitions
Pin
Function
Reserve JTAG
Keeps pins from being used and
changes the behavior of JTAG pins (no
pull-up on TMS)
Reserve
JTAG
Test
Reset
Regular I/O or JTAG reset with an
internal pull-up
Reserve Probe
Keeps pins from being used or regular
I/O
Table 1-6 Boundary-Scan Pin Configurations and
Functions
Mode
Designer
"Reserve JTAG"
Selection
TAP Controller
State
Dedicated (JTAG)
Checked
Any
Flexible (User I/O)
Unchecked
Test-Logic-Reset
Flexible (JTAG)
Unchecked
Any EXCEPT Test-
Logic-Reset
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相关代理商/技术参数 |
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|---|---|
| A54SX08A-FPQ208A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SX-A Family FPGAs |
| A54SX08A-FPQ208B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SX-A Family FPGAs |
| A54SX08A-FPQ208I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SX-A Family FPGAs |
| A54SX08A-FPQ208M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SX-A Family FPGAs |
| A54SX08A-FPQG208 | 功能描述:IC FPGA SX 12K GATES 208-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:SX-A 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14） |
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