参数资料
| 型号： | A54SX32A-1TQG144 |
| 厂商： | Microsemi SoC |
| 文件页数： | 26/108页 |
| 文件大小： | 0K |
| 描述： | IC FPGA SX 48K GATES 144-TQFP |
| 标准包装： | 60 |
| 系列： | SX-A |
| LAB/CLB数： | 2880 |
| 输入/输出数： | 113 |
| 门数： | 48000 |
| 电源电压： | 2.25 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-TQFP（20x20） |
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SX-A Family FPGAs
2- 4
v5.3
Table 2-8 AC Specifications (5 V PCI Operation)
Symbol
Parameter
Condition
Min.
Max.
Units
IOH(AC)
Switching Current High
0 < VOUT ≤ 1.4
1
–44
–
mA
1.4
≤ V
OUT < 2.4
1, 2
(–44 + (VOUT – 1.4)/0.024)
–
mA
3.1 < VOUT < VCCI
1, 3
–
–
(Test Point)
VOUT = 3.1
3
––142
mA
IOL(AC)
Switching Current Low
VOUT ≥ 2.2
1
95
–
mA
2.2 > VOUT > 0.55
1
(VOUT/0.023)
–
mA
0.71 > VOUT > 0
1, 3
–
–
(Test Point)
VOUT = 0.71
3
–
206
mA
ICL
Low Clamp Current
–5 < VIN ≤ –1
–25 + (VIN + 1)/0.015
–
mA
slewR
Output Rise Slew Rate
0.4 V to 2.4 V load 4
15
V/ns
slewF
Output Fall Slew Rate
2.4 V to 0.4 V load 4
15
V/ns
Notes:
1. Refer to the V/I curves in Figure 2-1 on page 2-5. Switching current characteristics for REQ# and GNT# are permitted to be one half
of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#,
which are system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#,
which are open drain outputs.
2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than
toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up.
3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A
and B) are provided with the respective diagrams in Figure 2-1 on page 2-5. The equation defined maximum should be met by
design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.
4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any
point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter
with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum
parameters is now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not
required prior to revision 2.1 of the specification, there may be components in the market for some time that have faster edge
rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur and
should ensure that signal integrity modeling accounts for this. Rise slew rate does not apply to open drain outputs.
Output
Buffer
1/2 in. max.
50 pF
Pin
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| A54SX32A-1TQG144I | 功能描述:IC FPGA SX 48K GATES 144-TQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:SX-A 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A54SX32A-1TQG144M | 制造商:Microsemi Corporation 功能描述:FPGA SX-A 32K GATES 1800 CELLS 278MHZ 0.25UM/0.22UM 2.5V 144 - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 48K GATES 144TQFP 制造商:Microsemi Corporation 功能描述:IC FPGA 113 I/O 144TQFP |
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