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参数资料
| 型号： | A623308V-70SU |
| 厂商： | AMIC Technology Corporation |
| 英文描述： | 8K X 8 BIT CMOS SRAM |
| 中文描述： | 8K的× 8位CMOS的SRAM |
| 文件页数： | 8/13页 |
| 文件大小： | 130K |
| 代理商： | A623308V-70SU |
A623308 Series
PRELIMINARY
(December, 2002, Version 0.3)
7
AMIC Technology, Corp.
Timing Waveforms (continued)
Read Cycle 3
(1, 3, 4)
t
CLZ 5
t
ACE
t
CHZ 5
CE
D
OUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled, CE = V
IL
.
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. Transition is measured
±
500mV from steady state. This parameter is sampled and not 100% tested.
Write Cycle 1
(6)
(Write Enable Controlled)
t
WC
Address
CE
D
IN
t
OW 7
t
DH
t
DW
t
WHZ 7
t
WP2
t
AS1
(4)
t
CW5
t
AW
t
WR3
WE
D
OUT
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