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参数资料
| 型号： | A627308 |
| 厂商： | AMIC Technology Corporation |
| 英文描述： | 128K X 8 BIT CMOS SRAM |
| 中文描述： | 128K的× 8位CMOS的SRAM |
| 文件页数： | 6/16页 |
| 文件大小： | 250K |
| 代理商： | A627308 |
AC Characteristics
(T
A
= 0
°
C to + 70
°
, VCC = 5.0V
±
10%)
A627308 Series
PRELIMINARY
(February, 2001, Version 0.2)
5
AMIC Technology, Inc.
Symbol
Parameter
A627308-70S
Unit
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
70
-
ns
t
AA
Address Access Time
-
70
ns
t
ACE1
Chip Enable Access Time
CE1
-
70
ns
t
ACE2
CE2
-
70
ns
t
OE
Output Enable to Output Valid
-
35
ns
t
CLZ1
Chip Enable to Output in Low Z
CE1
10
-
ns
t
CLZ2
CE2
10
-
ns
t
OLZ
Output Enable to Output in Low Z
5
-
ns
t
CHZ1
Chip Disable to Output in High Z
CE1
0
25
ns
t
CHZ2
CE2
0
25
ns
t
OHZ
Output Disable to Output in High Z
0
25
ns
t
OH
Output Hold from Address Change
10
-
ns
Write Cycle
t
WC
Write Cycle Time
70
-
ns
t
CW
Chip Enable to End of Write
60
-
ns
t
AS
Address Setup Time
0
-
ns
t
AW
Address Valid to End of Write
60
-
ns
t
WP
Write Pulse Width
50
-
ns
t
WR
Write Recovery Time
0
-
ns
t
WHZ
Write to Output in High Z
0
30
ns
t
DW
Data to Write Time Overlap
30
-
ns
t
DH
Data Hold from Write Time
0
-
ns
t
OW
Output Active from End of Write
5
-
ns
Notes: t
CHZ1
, t
CHZ2
, t
OHZ
and t
WHZ
are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
相关PDF资料 |
PDF描述 |
|---|---|
| A627308M | 128K X 8 BIT CMOS SRAM |
| A627308M-70S | 128K X 8 BIT CMOS SRAM |
| A627308V | 128K X 8 BIT CMOS SRAM |
| A627308X | 128K X 8 BIT CMOS SRAM |
| A6273KLW | 8-BIT LATCHED DMOS POWER DRIVER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A627308M | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:128K X 8 BIT CMOS SRAM |
| A627308M-70S | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:128K X 8 BIT CMOS SRAM |
| A627308V | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:128K X 8 BIT CMOS SRAM |
| A627308V-70S | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:128K X 8 BIT CMOS SRAM |
| A627308X | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:128K X 8 BIT CMOS SRAM |
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