参数资料
型号: A6280EA-T
厂商: Allegro Microsystems Inc
文件页数: 7/14页
文件大小: 0K
描述: IC LED DRIVER PWM CONTROL 16-DIP
标准包装: 10,000
恒定电流:
拓扑: 线性,PWM
输出数: 3
内部驱动器:
类型 - 次要: RGB
频率: 5MHz
电源电压: 4.75 V ~ 17 V
输出电压: 1 V ~ 3 V
安装类型: 通孔
封装/外壳: 16-DIP(0.300",7.62mm)
供应商设备封装: 16-DIP
包装: 管件
工作温度: -40°C ~ 85°C
产品目录页面: 1141 (CN2011-ZH PDF)
其它名称: 620-1256
A6280
3-Channel Constant-Current LED Driver
with Programmable PWM Control
Functional Description
Shift Register
The A6280 has a 31 bit shift register that loads data through the
SDI (Serial Data In) pin. The shift register operates by a first-in
first-out (FIFO) method. The most significant bit (MSB, bit 30)
is the first bit shifted in and the least significant bit (LSB, bit 0)
is shifted in last. The serial data is clocked by a rising edge of
the CI (Clock In) pin. The SDO (Serial Data Out) pin is updated
to the state of bit 30 on the falling edge of the CI pin. This will
prevent any race conditions and erroneous data that might occur
while propagating information through multiple A6280 that are
daisy chained together. The contents of the shift register will
continue to propagate on every rising edge of the CI pin. The
information in the shift register is latched on a rising edge of the
LI (Latch In) pin. The LI pin must be brought low before the ris-
ing edge of the next clock pulse, to avoid latching erroneous data.
The latched data remains latched on a rising OEI (Output Enable
In) signal.
Output Buffers
The A6280 is designed to allow daisy chaining many A6280s
together. It can pass the clock, data, latch, and output enable
signals from one A6820 to the next without any loss of data due
to duty cycle skewing or signal degradation.
The A6820 is equipped with output buffers that allow the data
signals to travel over long distances through strings of A6280s
without the need for extra driving hardware. The A6280 drives
these signals to TTL levels. Each of the A6280 inputs have a cor-
responding buffered output:
? CI (Clock In) pin to CO (Clock Out) pin
? LI (Latch In) pin to LO (Latch Out) pin
? OEI (Output Enable In) pin to OEO (Output Enable Out) pin
? SDI (Serial Data In) pin to SDO (Serial Data Out) pin
The CO (Clock Out) pin is driven by an internal one-shot circuit.
When the CI pin detects an edge rising through the input thresh-
old, the one-shot circuitry drives the CO pin high for 100 ns. The
CI pin input threshold has hysteresis to prevent false triggering
of the CO signal. The implementation on the one-shot solution
allows many A6280s to be daisy chained together with a consis-
tent clock signal throughout the entire chain without degradation
or loss of synchronicity to the data line.
SDI
Shift Register
0 to 6
7 to 8
9
10 to 16
17 to 19
20 to 26
27
28 to 29
30
SDO
CI
LI
Latched Registers
100 ns
One-Shot
CO
LO
Current Clock
Scalar 0 Divider Unused
7 Bits 2 Bits 1 Bit
Current
Scalar 1
7 Bits
Unused
3 Bits
Current
Scalar 2 Unused
7 Bits 1 Bit
Test
Bits
2 Bits
Bit 30
“1”
OEI
PWM Counter 0
10 Bits
PWM Counter 1
10 Bits
PWM Counter 2
10 Bits
Bit 30
“0”
OEO
R EXT
REXT
VIN
+5 V
Regulator
Current
Regulator 0
Current
Regulator 1
Current
Regulator 2
VREG
OUT0
OUT1
OUT2
PGND
LGND
Figure 4. Functional Diagram
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
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