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| 型号： | A6280EESTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 9/14页 |
| 文件大小： | 0K |
| 描述： | IC LED DRIVER PWM CONTROL 16-QFN |
| 标准包装： | 1 |
| 恒定电流： | 是 |
| 拓扑： | 线性，PWM |
| 输出数： | 3 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 通用 |
| 类型 - 次要： | RGB |
| 频率： | 5MHz |
| 电源电压： | 4.75 V ~ 17 V |
| 输出电压： | 1 V ~ 3 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-WFQFN 裸露焊盘 |
| 供应商设备封装： | 16-QFN/MLP 裸露焊盘（3x3） |
| 包装： | 标准包装 |
| 工作温度： | -40°C ~ 85°C |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1179-6 |
A6280
3-Channel Constant-Current LED Driver
with Programmable PWM Control
and external voltage regulators. For 5 V supplies, connect VIN
to VREG externally. Note: When using 5 V supplies, ensure that
VIN does not exceed the absolute maximum rating of the VREG
pin (6 V).
The VREG pin is used by the internal linear regulator to connect
to a bypass capacitor. This pin is for internal use only and is not
intended as an external power source. There should be a 1.0 μ F,
10 V ceramic capacitor connected between the VREG pin and
LGND. The capacitor should be located as close to the VREG
pin as possible.
Dot Correction Control
The A6280 can further control the maximum output current for
each output by setting the three 7-bit dot correction registers
with scale data that ranges from 36.5% to 100% of the overall
maximum output current that is set by the R EXT resistor. This
feature is useful because not every type of LED (red, green, or
blue, for example) has the same level of brightness for a given
current, and the brightness could be different even from LED to
LED of the same type. By scaling the output currents so that all
the LEDs have matched intensities, the application will have full
color depth when using the PWM counters. The dot correction
current can be calculated by the following equation:
I OUT n = I OUT n (max) × (Scale n / 2 + 36.5) / 100
Where Scale n is in the range 0 to 127, as shown in the following
table:
I OUT /I OUT (max)
Scale (%)
0 36.5
Refer to figure 6 for the bit configurations for the scalar registers.
The dot correction data in the shift register is latched on a rising
edge of the LI (Latch In) pin. The dot correction data remains
latched on a rising OEI signal. The default output current when
the A6280 is powered-up or recovers from a UVLO is 36.5% of
the current set by the R EXT resistor.
Package Power Dissipation
The maximum allowable package power dissipation is deter-
mined as:
P D (max) = (150 – T A ) / R ? JA .
The actual package power dissipation is:
P D(act) = DC 0 × V DS0 × I OUT0
+ DC 1 × V DS1 × I OUT1
+ DC 2 × V DS2 × I OUT2 + V IN × I IN .
where DC i is the PWM duty cycle for channel i , and I OUTi is the
output current for channel i , determined by the dot correction
current for that channel and REXT.
When calculating power dissipation, the total number of avail-
able device outputs is usually used for the worst-case situation
(i.e., displaying all 3 LEDs at 100% DC).
Thermal Shutdown (TSD)
When the junction temperature of the A6280 reaches the thermal
shutdown temperature threshold, T JTSD (165°C typical), the
outputs will shut off until the junction temperature cools down
1
2
...
127
37.0
37.5
...
100
B its
below the recovery threshold, T JTSD – ? T J ( 15°C typical). The
shift register and output latches will remain active during the
TSD event. Therefore there is no need to reset the data in the
output latches.
0 1 2 3 4 5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
28
29
30 a
PWM Counter 0
PWM Counter 1
PWM Counter 2
Address “0”
Dot Correction
Register 0
Clock
Mode
0
Dot Correction
Register 1
0 0 0
Dot Correction
Register 2
0 ATB b ATB b Address “1”
a Selects
b Allegro
which word is written to: Dot Correction/Clock Mode selection or PWM counter.
Test Bit (ATB). Reserved for Allegro internal testing. Always set to zero (0) in the application.
Figure 6. Register Configuration
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
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