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| 型号： | A6282ELW-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 10/13页 |
| 文件大小： | 0K |
| 描述： | IC LED DRIVER LINEAR 24-SOIC |
| 标准包装： | 31 |
| 恒定电流： | 是 |
| 拓扑： | 线性 |
| 输出数： | 16 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 背光 |
| 类型 - 次要： | 颜色，白色 LED |
| 频率： | 30MHz |
| 电源电压： | 3 V ~ 5.5 V |
| 输出电压： | 12V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 管件 |
| 工作温度： | -40°C ~ 85°C |
| 其它名称： | 620-1223-5 |
A6282
16-Channel Constant-Current LED Driver
Application Information
Load Supply Voltage (V LED )
This device is designed to operate with driver voltage drops (V DS )
of 1.0 to 3.0V. If higher voltages are dropped across the driver,
package power dissipation will increase. To minimize package
power dissipation, it is recommended to use the lowest possible
load supply voltage, V LED , or to set a series voltage drop, V DROP ,
according to the following formula:
V DROP = V LED – V F – V DS ,
where V F is the LED forward voltage. For reference, typical LED
forward voltages are:
1. Place the REXT resistor as close as possible to the REXT
pin and GND pin. This will minimize parasitic inductance and
capacitance.
2. Use a separate line to the device GND pin for REXT, and sepa-
rate lines for the decoupling capacitors. The lines should join at
ground. This star grounding will improve output load regulation
and minimize any chance of oscillation.
The REXT ground line should carry only the small current from
the internal voltage reference at REXT. The high AC currents
flowing through the decoupling capacitors and their resistive and
inductive PCB lines cause noise (ground bounce) on the capacitor
LED Type
White
Blue
Green
Yellow
Amber
Red
Infrared
UV
V F (V)
3.5 to 4.0
3.0 to 5.5
1.8 to 2.5
2.0 to 2.5
1.9 to 3.0
1.6 to 2.5
1.2 to 1.8
3.0 to 4.0
ground lines. Such noise could disturb the reference voltage at
REXT and promote oscillation. Connect the exposed thermal pad
of the ES and LP packages to the power ground, along with the
decoupling capacitors, and not to the ground line for REXT.
3. Keep the output drive lines (OUT0 through OUT15) away
from the REXT pin to avoid coupling of the output signal into
the reference for the current sources. Output lines should not run
adjacent to the REXT pin or directly under the REXT pin.
V DROP = I O × R DROP for a single driver, for a Zener diode (V Z ),
or for a series string of silicon diodes (approximately 0.7 V per
diode) for a group of drivers (these configurations are shown
in the figure below). If the available voltage source will cause
unacceptable power dissipation and series resistors or diodes are
undesirable, a voltage regulator can be used to provide V LED .
Pattern Layout
To save pins and board space, the A6282 uses one pin for both
logic ground and power ground. Therefore, achieving optimal
performance requires careful attention to layout. Following the
suggestions below will improve the analog performance and logic
4. Use decoupling capacitors on the VDD pin and the LED sup-
ply bus. Place the logic decoupling capacitor (0.1 μ F, one for
each A6282) as close as possible to the VDD pin. Use at least one
10 μ F capacitor from the LED supply line to device ground for at
least every two A6282s.
5. Use multilayer boards if possible.
Package Power Dissipation
The maximum allowable package power dissipation based on
package type is determined by:
P D(max) = (150 – T A ) / R ? JA ,
noise immunity.
V LED
V LED
V LED
where R ? JA is the thermal resistance of the package, determined
experimentally. Power dissipation levels based on the package are
shown in the Thermal Characteristics table.
The actual package power dissipation is determined by:
V DROP
V DROP
V DROP
P D(act) = DC × (V DS × I O × 16) + (V DD × I DD ) ,
where DC is the duty cycle. The value 16 is the maximum
number of available device outputs, representing the worst-case
scenario (displaying all 16 LEDs). When the load supply voltage,
V F
V DS
V F
V DS
Typical application voltage drops
V F
V DS
V LED , is greater than 3 to 5 V, and P D(act) > P D(max) , an external
voltage reducer (V DROP ) must be used (figure at left). Reducing
DC will also reduce power dissipation. The ES and LP packages
contain an exposed thermal pad on the bottom of the package
for enhanced heat dissipation. Connect this pad to a large power
ground plane using thermal vias. JEDEC documents JESD51-3
and JESD51-5 give suggestions for PCB and thermal via designs.
10
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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| A6282ELWTR-T | 功能描述:IC LED DRIVER LINEAR 24-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - LED 驱动器 系列:- 标准包装:1 系列:- 恒定电流:- 恒定电压:- 拓扑:PWM，切换式电容器（充电泵） 输出数:1 内部驱动器:是 类型 - 主要:背光 类型 - 次要:白色 LED 频率:642kHz 电源电压:2.7 V ~ 5.5 V 输出电压:5V 安装类型:表面贴装 封装/外壳:10-VFDFN 裸露焊盘 供应商设备封装:10-VSON 包装:剪切带 (CT) 工作温度:-30°C ~ 85°C 产品目录页面:1371 (CN2011-ZH PDF) 其它名称:BD1603NUV-E2CT |
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