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参数资料
| 型号： | A6402 |
| 元件分类： | 通信、网络模块及开发工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 电信/数据通信 |
| 文件页数： | 2/8页 |
| 文件大小： | 241K |
| 代理商： | A6402 |
58
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Ports
Table 1
shows the input and output ports for the
a6402
.
Table 1. a6402 Ports
Name
Type
Polarity
Description
cls1
cls2
Input
–
Character length select bits. These bits determine the length of the data
word.
00 = 5-bit word format
01 = 6-bit word format
10 = 7-bit word format
11 = 8-bit word format
Control register load. Controls how the data word is loaded into the control
register.
Data received reset. Clears the
dr
output.
Even parity enable. When high, even parity; when low, odd parity.
Master reset. Clears the
pe
,
fe
,
dr
, and
and
tbre
outputs.
Parity inhibit. When
pi
is asserted, parity is neither generated nor checked.
Receiver register clock. Operates at 16 times the receive data rate.
Receiver register input. Serial input data.
Stop bit select. When high,
sbs
generates 2 stop bits (1.5 stop bits for 5-bit
format); when low,
sbs
generates 1 stop bit.
Transmitter buffer register load. Enables load of the transmitter buffer
register.
Transmitter buffer register input bus.
Transmitter register clock. Operates at 16 times the transmit data rate.
Data received. Indicates that a data word has been transferred to the
receiver buffer register.
Framing error. Asserted when the expected stop bit(s) is not detected.
Overrun error. Asserted when data in the receiver buffer register is
overwritten while the
dr
output is still asserted.
Parity error. Set when the calculated parity does not match the received
parity. When
pi
is asserted,
pe
is set low.
Receiver buffer register bus.
Transmitter buffer register empty. Indicates that the transmitter buffer
register is empty.
Transmitter register empty. Indicates that the data word is completely
transmitted out of the transmitter register.
Transmitter register output. Serial output data.
crl
Input
High
ndrr
Input
Input
Input
Low
High/low
High
epe
mr
oe
outputs, and asserts the
tre
pi
Input
Input
Input
Input
High
rrc
–
–
rri
sbs
High/low
ntbrl
Input
Low
tbr[7..0]
Input
Input
Output
–
–
trc
dr
High
fe
Output
Output
High
High
oe
pe
Output
High/low
rbr[7..0]
Output
Output
–
tbre
High
tre
Output
High
tro
Output
–
相关PDF资料 |
PDF描述 |
|---|---|
| a6402 | Universal Asynchronous Receiver/Transmitter(通用异步接收/传送器) |
| A65-1 | Analog IC |
| A655NV400C5 | Interface IC |
| 697NV400C5 | Microprocessor Supervisory Circuits |
| 697NV400M5 | Microprocessor Supervisory Circuits |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A6-403-002 | 制造商:Hecon / Danaher 功能描述: |
| A6-40-314-10 | 制造商:Southco 功能描述: |
| A6-404-025 | 制造商:HECON / DANAHER 功能描述: 制造商:Hecon / Danaher 功能描述: |
| A6-404-035 | 制造商:HECON / DANAHER 功能描述: 制造商:Hecon / Danaher 功能描述: |
| A6-404-041 | 制造商:HECON / DANAHER 功能描述: |
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