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参数资料
| 型号： | A6850KLTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 8/12页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH INTERFACE 2CHAN 8-SOIC |
| 标准包装： | 1 |
| 类型： | 霍尔效应开关 |
| 输入类型： | 电压 |
| 输出类型： | 电压 |
| 接口： | 2 线串口 |
| 电流 - 电源： | 5mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1185-6 |
Dual Channel Switch Interface IC
A6850
5
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Description
SENSE Pin Outputs
The A6850 divides the OUTPUTx pin current by 10 and mirrors
it onto the corresponding SENSEx pin. Putting sense resistors,
RSENSE , from these pins to ground will create a voltage that
can be read by an ADC (analog-to-digital converter). The value
of RSENSE should be chosen so that the voltage drop across the
sense resistor (VRSENSE) does not exceed the maximum voltage
rating of the ADC. For further protection of the ADC, an external
clamping circuit, such as a Zener diode, can be used to clamp any
transient current spikes that may occur on the output that would
be translated onto the SENSE pins.
The sense current is one tenth of the output current, plus an offset
current. This offset current is consistent across the whole range
of the output current. The sense current can be calculated by the
following formula:
ISENSEx = (IOUTPUTx / 10) + ISENSE(ofs) .
(1)
The sense resistor must also be chosen to meet the voltage limits
on the sense pin (see Electrical Characteristics table).
Output Current Limit
The A6850 limits the output current to a maximum current of
IOUTPUTM. The output current will remain at the current limit
until the output load is reduced or the A6850 goes into thermal
shutdown.
The high output current limit allows the bypass capacitor, CBYP,
on the Hall sensor IC to charge up quickly. This allows a high slew
rate on the VCC pin of the Hall sensor IC, ensuring that the sensor
IC Power-On State will be correct. See the Applications Informa-
tion section for schematic diagrams and power calculations.
Output Faults
The A6850 withstands short-to-ground or short-to-battery of the
OUTPUTx pins. In the case of short-to-ground, current is held to
the current limit (IOUTPUTM).
If VOUTPUTx > (VIN + 0.7 V) during a short-to-battery event, the
A6850 monitors VOUTPUTx and disables the outputs. Because the
protection circuitry requires a finite amount of time to disable the
outputs, a bypass capacitor of 1 μF is necessary on VIN. Although
OUTPUTx sinks current into the A6850 in this state, the reverse
current is shunted to ground and does not appear on the VIN pin.
Overvoltage Protection
The A6850 has built-in overvoltage protection against a load
dump on the supply bus. In the case of a load dump, or when VIN
is connected to the battery supply bus and VIN rises above the
overvoltage threshold, VOVP, the A6850 will shut off the outputs.
Sleep Mode
Low-leakage or sleep modes are required in automotive applica-
tions to minimize battery drain when the vehicle is parked. The
A6850 enters sleep mode when both ENABLE pins are low. In
sleep mode, the internal regulators and all other internal circuitry
are disabled.
When enabling an output, the part must first come out of sleep
mode. Consequently, the wake-up time amounts to a propagation
delay before the outputs turn on. Also, the ENABLE pins do not
switch with hysteresis until the regulators stabilize.
After the internal regulators stabilize, internal circuitry is enabled
and the outputs turn on, as shown in figure 3. As long as one
ENABLE pin is held high, the A6850 operates with hysteresis.
Figure 3. Activation Timing Diagram. Exiting Sleep mode via ENABLE
signal to output waveform.
RegOk
VREG
OUTPUT
ENABLE
V
ENABLEL
> t
ON
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