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| 型号： | A82DL1632TG-70 |
| 厂商： | AMIC Technology Corporation |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| 中文描述： | 堆叠式多芯片封装（MCP）闪存和SRAM，A82DL16x2T（ü）16兆位（2Mx8 Bit/1Mx16位）的CMOS 3.3伏只，同时闪电行动 |
| 文件页数： | 25/57页 |
| 文件大小： | 883K |
| 代理商： | A82DL1632TG-70 |
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A82DL16x2T(U) Series
PRELIMINARY
(May, 2005, Version 0.1)
24
AMIC Technology, Corp.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not require the system to preprogram prior to erase.
The Embedded Erase algorithm automatically preprograms
and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide
any controls or timings during these operations. Table 12
shows the address and data requirements for the chip erase
command sequence.
When the Embedded Erase algorithm is complete, that bank
returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using I/O
7
, I/O
6
, I/O
2
, or RY/
BY
. Refer to the
Write Operation Status section for information on these
status bits.
Any commands written during the chip erase operation are
ignored. However, note that a hardware reset immediately
terminates the erase operation. If that occurs, the chip erase
command sequence should be reinitiated once that bank has
returned to reading array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase operation.
Refer to the Erase and Program Operations tables in the AC
Characteristics section for parameters, and Figure 17 section
for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock cycles
are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table
12 shows the address and data requirements for the sector
erase command sequence.
The device does not require the system to preprogram prior
to erase. The Embedded Erase algorithm automatically
programs and verifies the entire memory for an all zero data
pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-
out of 50 μs occurs. During the time-out period, additional
sector addresses and sector erase commands within the
bank may be written. Loading the sector erase buffer may be
done in any sequence, and the number of sectors may be
from one sector to all sectors. The time between these
additional cycles must be less than 50μs, otherwise erasure
may begin. Any sector erase address and command
following the exceeded time-out may or may not be accepted.
It is recommended that processor interrupts be disabled
during this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. Any command other than Sector Erase
or Erase Suspend during the time-out period resets that bank
to reading array data. The system must rewrite the command
sequence and any additional addresses and commands.
The system can monitor I/O
3
to determine if the sector erase
timer has timed out (See the section on I/O
3
: Sector Erase
Timer.). The time-out begins from the rising edge of the final
WE
pulse in the command sequence.
When the Embedded Erase algorithm is complete, the bank
returns to reading array data and addresses are no longer
latched. Note that while the Embedded Erase operation is in
progress, the system can read data from the non-erasing
bank. The system can determine the status of the erase
operation by reading I/O
7
, I/O
6
, I/O
2
, or RY/
BY
in the erasing
bank.
Refer to the Write Operation Status section for information on
these status bits.
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are ignored.
However, note that a hardware reset immediately terminates
the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once that bank has
returned to reading array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase operation.
Refer to the Erase and Program Operations tables in the AC
Characteristics section for parameters, and Figure 17 section
for timing diagrams
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to
interrupt a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. This
command is valid only during the sector erase operation,
including the 50 μs time-out period during the sector erase
command sequence. The Erase Suspend command is
ignored if written during the chip erase operation or
Embedded Program algorithm.
When the Erase Suspend command is written during the
sector erase operation, the device requires a maximum of 20
μs to suspend the erase operation. However, when the Erase
Suspend command is written during the sector erase time-
out, the device immediately terminates the time-out period
and suspends the erase operation.
After the erase operation has been suspended, the bank
enters the erase-suspend-read mode. The system can read
data from or program data to any sector not selected for
erasure. (The device “erase suspends” all sectors selected
for erasure.) Reading at any address within erase-suspended
sectors produces status information on I/O
7
–I/O
0
. The system
can use I/O
7
, or I/O
6
and I/O
2
together, to determine if a
sector is actively erasing or is erase-suspended. Refer to the
Write Operation Status section for information on these
status bits.
After an erase-suspended program operation is complete,
the bank returns to the erase-suspend-read mode. The
system can determine the status of the program operation
using the I/O
7
or I/O
6
status bits, just as in the standard Byte
Program operation. Refer to the Write Operation Status
section for more information.
In the erase-suspend-read mode, the system can also issue
the autoselect command sequence. Refer to the Autoselect
Mode and Autoselect Command Sequence sections for
details.
To resume the sector erase operation, the system must write
the Erase Resume command. The bank address of the
erase-suspended bank is ignored when writing this command.
Further writes of the Resume command are ignored. Another
Erase Suspend command can be written after the chip has
resumed erasing.
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| A82DL1642TG-70 | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1632TG-70F | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1642TG-70F | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1632TG-70I | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1642TG-70I | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A82DL1632TG-70F | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1632TG-70I | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1632TG-70IF | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1632TG-70U | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1632TG-70UF | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
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