- 您现在的位置：买卖IC网 > PDF目录375159 > A82DL1632TG-70IF (AMIC Technology Corporation) Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash PDF资料下载
参数资料
| 型号： | A82DL1632TG-70IF |
| 厂商： | AMIC Technology Corporation |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| 中文描述： | 堆叠式多芯片封装（MCP）闪存和SRAM，A82DL16x2T（ü）16兆位（2Mx8 Bit/1Mx16位）的CMOS 3.3伏只，同时闪电行动 |
| 文件页数： | 27/57页 |
| 文件大小： | 883K |
| 代理商： | A82DL1632TG-70IF |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页当前第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页
A82DL16x2T(U) Series
PRELIMINARY
(May, 2005, Version 0.1)
26
AMIC Technology, Corp.
Command Definitions
Table 12. A82DL16x2T(U) Command Definitions
Bus Cycles (Notes 2–5)
Third
Addr
Data
(BA)555
90
First
Second
Addr
2AA
555
2AA
555
2AA
555
2AA
555
2AA
555
2AA
555
2AA
555
PA
XXX
2AA
555
2AA
555
Fourth
Addr
Fifth
Sixth
Command
Sequence
(Note 1)
C
Addr
RA
XXX
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
XXX
XXX
555
AAA
555
AAA
XXX
XXX
55
AA
Data
RD
F0
Data
Data
Addr
2AA
555
2AA
555
Data
Addr
Data
Read (Note 6)
Reset (Note 7)
1
1
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Manufacturer ID
4
AA
55
(BA)AAA
(BA)X00
37
(BA)555
(BA)X01
Device ID
4
AA
55
(BA)AAA
555
AAA
90
(BA)X02
X03
X06
(see
Table5)
Continuation ID
4
AA
55
90
7F
(BA)555
(SA)
A
Sector Protect Verify
(Note 9)
4
AA
55
(BA)AAA
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
90
(SA)X04
00/01
Command Temporary
Sector Unprotect(Note 15)
3
AA
55
77
Program
4
AA
55
A0
PA
PD
Unlock Bypass
3
AA
55
20
Unlock Bypass Program (Note 10)
Unlock Bypass Reset (Note 11)
2
2
A0
90
PD
00
Word
Byte
Word
Byte
555
AA A
555
AAA
555
AAA
Chip Erase
6
AA
55
80
AA
55
10
55
80
Sector Erase
6
AA
AA
55
SA
30
Erase Suspend (Note 12)
Erase Resume (Note 13)
1
1
B0
30
Word
Byte
CFI Query (Note 14)
1
98
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the
WE
or
CE_F
pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of
WE
or
CE_F
pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19 - A12 select a unique sector.
BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles.
4. Data bits I/O
15
-I/O
8
are don’t care in command sequences. Except for RD and PD.
5. Unless otherwise noted, address bits A19-A11 are don’t cares.
6. No unlock or command cycles required when bank is reading array data.
7. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if I/O
5
goes high (while the bank is providing status information).
8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain
the manufacture ID, or device ID information. Data bits I/O
15
-I/O
8
are don’t care. See the Autoselect Command Sequence
section for more information.
9. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block.
10. The Unlock Bypass command is required prior to the Unlock Bypass Program Command.
11. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode.
12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase operation, and require the bank address.
13. The Erase Resume command is valid only during the Erase.
14. Command is valid when device is ready to read array data or when device is in autoselect mode.
15. Once reset command is applied, software temporary unprotect is exit to return read array data. But under erase suspend
condition, this command is still effective even a reset command has been applied. The reset command which can deactivate
the software temporary unprotect command is useful only after the erase command is complete.
相关PDF资料 |
PDF描述 |
|---|---|
| A82DL1642TG-70IF | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1632TG-70U | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1642TG-70U | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1632UG-70 | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1642UG-70 | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A82DL1632TG-70U | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1632TG-70UF | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1632UG-70 | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1632UG-70F | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1632UG-70I | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
发布紧急采购，3分钟左右您将得到回复。