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| 型号： | A82DL1642TG-70 |
| 厂商： | AMIC Technology Corporation |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| 中文描述： | 堆叠式多芯片封装（MCP）闪存和SRAM，A82DL16x2T（ü）16兆位（2Mx8 Bit/1Mx16位）的CMOS 3.3伏只，同时闪电行动 |
| 文件页数： | 30/57页 |
| 文件大小： | 883K |
| 代理商： | A82DL1642TG-70 |
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A82DL16x2T(U) Series
PRELIMINARY
(May, 2005, Version 0.1)
29
AMIC Technology, Corp.
I/O
2
: Toggle Bit II
The "Toggle Bit II" on I/O
2
, when used with I/O
6
, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the final
WE
pulse in the command sequence.
I/O
2
toggles when the system reads at addresses within those
sectors that have been selected for erasure. (The system may
use either
OE
or
CE_F
to control the read cycles.) But I/O
2
cannot distinguish whether the sector is actively erasing or is
erase-suspended. I/O
6
, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information.
Refer to Table 8 to compare outputs for I/O
2
and I/O
6
.
Figure 6 shows the toggle bit algorithm in flowchart form, and
the section " I/O
2
: Toggle Bit II" explains the algorithm. See
also the " I/O
6
: Toggle Bit I" subsection. Figure 20 shows the
toggle bit timing diagram. Figure 21 shows the differences
between I/O
2
and I/O
6
in graphical form.
Reading Toggle Bits I/O
6
, I/O
2
Refer to Figure 6 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O
7
-I/O
0
at least twice in a row to determine whether a toggle
bit is toggling. Typically, a system would note and store the
value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can
read array data on I/O
7
-I/O
0
on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O
5
is high (see the section
on I/O
5
). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as I/O
5
went high. If the toggle bit
is no longer toggling, the device has successfully completed
the program or erase operation. If it is still toggling, the device
did not complete the operation successfully, and the system
must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and I/O
5
has not gone high. The
system may continue to monitor the toggle bit and I/O
5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Figure
6).
I/O
5
: Exceeded Timing Limits
I/O
5
indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions I/O
5
produces a "1." This is a failure condition that
indicates the program or erase cycle was not successfully
completed.
The device may output a “1” on I/O
5
if the system tries to
program a “1” to a location that was previously programmed
to “0.” Only an erase operation can change a “0” back to a
“1.” Under this condition, the device halts the operation, and
when the timing limit has been exceeded, I/O
5
produces a
“1.” .
Under both these conditions, the system must write the reset
command to return to reading array data (or to the erase-
suspend-read mode if a bank was previously in the erase-
suspend-program mode).
I/O
3
: Sector Erase Timer
After writing a sector erase command sequence, the system
may read I/O
3
to determine whether or not an erase
operation has begun. (The sector erase timer does not apply
to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies after
each additional sector erase command. When the time-out is
complete, I/O
3
switches from "0" to "1." The system may
ignore I/O
3
if the system can guarantee that the time
between additional sector erase commands will always be
less than 50
μ
s. See also the "Sector Erase Command
Sequence" section.
After the sector erase command sequence is written, the
system should read the status on I/O
7
(
Data
Polling) or I/O
6
(Toggle Bit 1) to ensure the device has accepted the
command sequence, and then read I/O
3
. If I/O
3
is "1", the
internally controlled erase cycle has begun; all further
commands (Except Erase Suspend) are ignored until the
erase operation is complete. If I/O
3
is "0", the device will
accept additional sector erase commands. To ensure the
command has been accepted, the system software should
check the status of I/O
3
prior to and following each
subsequent sector erase command. If I/O
3
is high on the
second status check, the last command might not have been
accepted.
Table 13 shows the status of I/O
3
relative to the other status
bits.
相关PDF资料 |
PDF描述 |
|---|---|
| A82DL1632TG-70F | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1642TG-70F | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1632TG-70I | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1642TG-70I | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1632TG-70IF | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A82DL1642TG-70F | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1642TG-70I | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1642TG-70IF | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1642TG-70U | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1642TG-70UF | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
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