- 您现在的位置：买卖IC网 > PDF目录375159 > A82DL1642TG-70F (AMIC Technology Corporation) Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash PDF资料下载
参数资料
| 型号： | A82DL1642TG-70F |
| 厂商： | AMIC Technology Corporation |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| 中文描述： | 堆叠式多芯片封装（MCP）闪存和SRAM，A82DL16x2T（ü）16兆位（2Mx8 Bit/1Mx16位）的CMOS 3.3伏只，同时闪电行动 |
| 文件页数： | 12/57页 |
| 文件大小： | 883K |
| 代理商： | A82DL1642TG-70F |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页当前第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页
A82DL16x2T(U) Series
PRELIMINARY
(May, 2005, Version 0.1)
11
AMIC Technology, Corp.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for t
ACC
+30ns. The automatic
sleep mode is independent of the
CE_F
,
WE
and
OE
control signals. Standard address access timings provide
new data when addresses are changed. While in sleep
mode, output data is latched and always available to the
system. I
CC4_F
in the DC Characteristics table represents the
automatic sleep mode current specification.
RESET
: Hardware Reset Pin
The
RESET
pin provides a hardware method of resetting
the device to reading array data. When the system drives the
RESET
pin low for at least a period of t
RP
, the device
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the
RESET
pulse. The device also resets the
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the
RESET
pulse.
When
RESET
is held at VSS
±
0.3V, the device draws
CMOS standby current (I
CC4_F
). If
RESET
is held at V
IL
but
not within VSS
±
0.3V, the standby current will be greater.
The
RESET
pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
If
RESET
is asserted during a program or erase operation,
the RY/
BY
pin remains a “0” (busy) until the internal reset
operation is complete, which requires a time t
READY
(during
Embedded Algorithms). The system can thus monitor
RY/
BY
to determine whether the reset operation is
complete. If
RESET
is asserted when a program or erase
operation is not executing (RY/
BY
pin is “1”), the reset
operation is completed within a time of t
READY
(not during
Embedded Algorithms). The system can read data t
RH
after
the
RESET
pin return to V
IH
.
Refer to the AC Characteristics tables for
RESET
parameters and diagram.
Output Disable Mode
When the
OE
input is at V
IH
, output from the device is
disabled. The output pins are placed in the high impedance
state.
Table 2. A82DL16x2T(U) Device Bank Divisions
Bank 1
Bank 2
Device
Part Number
Megabits
Sector Sizes
Megabits
Sector Sizes
A82DL1622
2 Mbit
Eight 8 Kbyte/4 Kword,
three 64 Kbyte/32 Kword
14 Mbit
Twenty-eight
64 Kbyte/32 Kword
A82DL1632
4 Mbit
Eight 8 Kbyte/4 Kword,
seven 64 Kbyte/32 Kword
12 Mbit
Twenty-four
64 Kbyte/32 Kword
A82DL1642
8 Mbit
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
8 Mbit
Sixteen
64 Kbyte/32 Kword
相关PDF资料 |
PDF描述 |
|---|---|
| A82DL1632TG-70I | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1642TG-70I | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1632TG-70IF | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1642TG-70IF | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1632TG-70U | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A82DL1642TG-70I | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1642TG-70IF | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1642TG-70U | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1642TG-70UF | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1642UG-70 | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
发布紧急采购，3分钟左右您将得到回复。