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| 型号： | A82DL1642UG-70I |
| 厂商： | AMIC Technology Corporation |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| 中文描述： | 堆叠式多芯片封装（MCP）闪存和SRAM，A82DL16x2T（ü）16兆位（2Mx8 Bit/1Mx16位）的CMOS 3.3伏只，同时闪电行动 |
| 文件页数： | 29/57页 |
| 文件大小： | 883K |
| 代理商： | A82DL1642UG-70I |
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A82DL16x2T(U) Series
PRELIMINARY (May, 2005, Version 0.1)
28
AMIC Technology, Corp.
RY/
BY
: Ready/
Busy
The RY/
BY
is a dedicated, open-drain output pin that
indicates whether an Embedded algorithm is in progress or
complete. The RY/
BY
status is valid after the rising edge of
the final
WE
pulse in the command sequence. Since RY/
BY
is an open-drain output, several RY/
BY
pins can be tied
together in parallel with a pull-up resistor to VCC_F.
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is
ready to read array data (including during the Erase Suspend
mode), or is in the standby mode.
Table 13 shows the outputs for RY/
BY
.
I/O
6
: Toggle Bit I
Toggle Bit I on I/O
6
indicates whether an Embedded Program
or Erase algorithm is in progress or complete, or whether the
device has entered the Erase Suspend mode. Toggle Bit I
may be read at any address, and is valid after the rising edge
of the final
WE
pulse in the command sequence (prior to the
program or erase operation), and during the sector erase
time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause I/O
6
to toggle.
The system may use either
OE
or
CE_F
to control the read
cycles. When the operation is complete, I/O
6
stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O
6
toggles for
approximately 100
μ
s, then returns to reading array data. If not
all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O
6
and I/O
2
together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O
6
toggles. When the device
enters the Erase Suspend mode, I/O
6
stops toggling.
However, the system must also use I/O
2
to determine which
sectors are erasing or erase-suspended. Alternatively, the
system can use I/O
7
(see the subsection on " I/O
7
:
Data
Polling").
If a program address falls within a protected sector, I/O
6
toggles for approximately 1
μ
s after the program command
sequence is written, then returns to reading array data.
I/O
6
also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm is
complete.
Table 13 shows the outputs for Toggle Bit I on I/O
6
. Figure 6
shows the toggle bit algorithm. Figure 20 in the “AC
Characteristics” section shows the toggle bit timing diagrams.
Figure 23 shows the differences between I/O
2
and I/O
6
in
graphical form. See also the subsection on I/O
2
: Toggle Bit II.
START
Read I/O
7
-I/O
0
Toggle Bit
= Toggle
Program/Erase
Operation Not
Commplete, Write
Reset Command
Yes
Note:
The system should recheck the toggle bit even if I/O
5
=
”
1
"
because the toggle bit may stop toggling as I/O
5
changes to
“
1
”.
See the subsections on I/O
6
and I/O
2
for more information.
No
Read I/O
7
- I/O
0
Twice
I/O
5
= 1
Toggle Bit
= Toggle
Yes
Yes
Program/Erase
Operation Complete
No
No
Read I/O
7
-I/O
0
(Notes 1,2)
Figure 6. Toggle Bit Algorithm
(Note 1)
相关PDF资料 |
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|---|---|
| A82DL1632UG-70IF | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1642UG-70IF | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1632UG-70U | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1642UG-70U | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| A82DL1642UG-70IF | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1642UG-70U | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1642UG-70UF | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL1644 | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x4T(U) 16 Megabit (2Mx8 Bit/1Simultaneous Operation Flash Memory and 4M (256Kx16 Bit) S |
| A82DL1644TG-70 | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x4T(U) 16 Megabit (2Mx8 Bit/1Simultaneous Operation Flash Memory and 4M (256Kx16 Bit) S |
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