参数资料
型号: A8439EEJTR-T
厂商: Allegro Microsystems Inc
文件页数: 14/15页
文件大小: 0K
描述: IC CHARGER PHOTO FLASH 10-MLP
标准包装: 1
应用: 照相机闪光灯电容器充电器
电流 - 电源: 1.5mA
电源电压: 3 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘
供应商设备封装: 10-TDFN/MLP(3x3)
包装: 标准包装
产品目录页面: 1142 (CN2011-ZH PDF)
其它名称: 620-1203-6
A8439
Adjusting Output Voltage
Photoflash Capacitor Charger with IGBT Driver and Refresh
starts to ramp-up. It can be calculated as:
The A8439 senses output voltage continuously in order to provide
auto-refresh function. The output voltage can be adjusted by
V D_ Peak = V OUT + N × V BATT .
(4)
selecting proper values of the voltage divider resistors. Use the
The peak current of the rectifying diode, ID_Peak, is calculated as:
= OUT ? 1 .
following equation to calculate values for Rx (Ω):
R 1 + R 2 V
R 3 V FB
(3)
I D_ Peak = I Primary_Peak / N .
Input Capacitor Selection
(5)
R1 and R2 together need to have a breakdown voltage of at
least 300 V. A typical 0805 surface mount resistor has a 150 V
breakdown voltage rating. It is recommended that R1 and R2
have similar values to ensure an even voltage stress between
them. Recommended values are:
R1 = R2 = 10.0 M Ω (0805 or 1206)
R3 = 78.7 k Ω (0402 or 0603)
which together yield a stop voltage of 305 V.
If desired, larger resistance values may be used to reduce leakage
current from sensing network. (For example: R1=R2=15 M Ω ,
and R3 = 118 k Ω .)
Output Diode Selection
Choose the rectifying diode(s), D1, to have small parasitic
capacitance (short reverse recovery time) while satisfying the
reverse voltage and forward current requirements.
The peak reverse voltage of the diode, V D_Peak , occurs when the
internal MOSFET switch is closed, and the primary-side current
Recommended Components Table
Ceramic capacitors with X5R or X7R dielectrics are recom-
mended for the input capacitor, C2. It should be rated at least
4.7 μ F / 6.3 V to decouple the battery input, V BATT , at the primary
of the transformer. When using a separate bias, V BIAS , for the
A8439 VIN supply, connect at least a 0.1 μ F / 6.3 V bypass
capacitor to the VIN pin.
Layout Guidelines
Key to a good layout for the photoflash capacitor charger circuit
is to keep the parasitics minimized on the power switch loop
(transformer primary side) and the rectifier loop (secondary side).
Use short, thick traces for connections to the transformer primary
and SW pin.
Output voltage sensing circuit elements must be kept away from
switching nodes such as SW pin. It is important that the ˉDˉ ˉOˉ ˉNˉ ˉEˉ
signal trace and other signal traces be routed away from the trans-
former and other switching traces, in order to minimize noise
pickup. In addition, high voltage isolation rules must be followed
carefully to avoid breakdown failure of the circuit board.
Component Rating
Part Number
Source
C1, Input Capacitor
C2, Input Capacitor
0.1 μ F, ±10%, 16 V X7R ceramic
capacitor (0603)
4.7 μ F, ±10%, 10 V, X5R ceramic
capacitor (0805)
GRM188R71C104KA01D
LMK212BJ475KG
Murata
Taiyo Yuden
COUT, Photoflash Capacitor 330 V 100 μ F (or 19 to 180 μ F)
EPH-331ELL101B131S
Chemi-Con
D1, Output Diode
R1, R2, FB Resistors
R3, FB Resistor
T1, Transformer
2 x 250 V, 225 mA, 5 pF
10.0 M Ω , 1 / 8 W ±1% (0805)
78.7 k Ω 1 / 10 W ±1% (0603)
1:10.2, L Primary = 14.5 μ H
1:10.2, L Primary = 12 μ H
1:10, L Primary = 10.8 μ H
BAV23S
9C08052A1005FKHFT
9C06031A7872FKHFT
LDT565630T-002
T-16-024A
ST-532517A
Philips Semiconductor,
Fairchild Semiconductor
Yageo
Yageo
TDK
Tokyo Coil Engineering
Asatech
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
13
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