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| 型号： | AB-065 |
| 英文描述： | AB-065 - Superposition: The Hidden DAC Linearity Error |
| 中文描述： | 抗体- 065 -叠加：隐藏援线性误差 |
| 文件页数： | 1/2页 |
| 文件大小： | 90K |
| 代理商： | AB-065 |
CAREFUL LAYOUT TAMES SAMPLE-HOLD PEDESTAL ERRORS
by Anthony D. Wang
APPLICATION BULLE TIN
Mailing Address: PO Box 11400 Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd. Tucson, AZ 85706
Tel: (602) 746-1111 Twx: 910-952-111 Telex: 066-6491 FAX (602) 889-1510 Immediate Product Info: (800) 548-6132
FIGURE 2. Signal Coupling from Pin 14 to Pin 1 for Empty
Textool Socket.
S/H Input
2V/div
0V
0V
–Input
5mV/div
100
μ
s/div
In most sampling systems, the inherent characteristics of the
sample-hold dictate its overall performance. However, one
error source that sample-hold users do have under their
direct control is the external charge injection from the digital
control signal. This is known as charge transfer when mea-
sured in coulombs or as charge offset when measured in
volts. It is often also known as pedestal because of its
manifestation as a step change to the output. The culprit is
generally the parasitic capacitance between the digital con-
trol pin and some sensitive node(s) of the circuit.
Figure 1 shows the pinout of the SHC5320 with the addition
of a parasitic capacitor between pins 1 (inverting input) and
14 (the mode control pin). The inverting input is the closest
pin to the digital control signal that is sensitive enough to
amplify the parasitic feedthrough.
This is a typical coupling path because a convenient layout
approach would be to close the feedback loop between the
output and the inverting input by routing the trace under-
neath the device, where it could run too close to the mode
control pin.
spaced well away from the mode control line. Ideally, only
one of those two traces would route beneath the package.
Precautions should also be taken for two other pins that are
sensitive to coupling from the digital control pin. These are
pins 11 (external hold capacitor) and 8 (bandwidth control).
In case the sample-hold is configured for gain with a
feedback network, position the resistors such that their
junction with the inverting input occurs as close to that pin
as possible. If pedestal error still results, lower the feedback
network resistor values to reduce the sensitivity of this node
to parasitic coupling.
A more insidious parasitic path occurs when sockets are
used. Figure 2 shows the signal coupled across an empty
socket. The attenuation is roughly 50dB, but can still pro-
vide enough of a signal to cause a significant pedestal error.
This is suitably documented by the scope photo in Figure 3.
FIGURE 3. Pedestal Error Resulting from the Use of a
Textool Socket.
S/H Input
2V/div
0V
0V
V
5mV/div
100
μ
s/div
+
1
2
3
4
5
6
7
14
13
12
11
10
9
8
–Input
+Input
Offset Adjustment
Offset Adjustment
–V
CC
Reference
Common
Output
Mode Control
Supply Common
NC
External Hold
Capacitor
NC
+V
CC
Bandwidth Control
Cp
FIGURE 1. SCH5320 Pinout With Cp, Parasitic Capacitance.
Although the output of the sample-hold is considered a low
impedance node, this is not true at all frequencies. The
output impedance is kept low by the open-loop gain of the
amplifier. As the open-loop gain falls, the output impedance
rises and the amplifier is unable to swallow the high fre-
quency component of the parasitically coupled signal.
The correct layout technique would minimize the surface
area exposure between the inverting input node and the
digital sample-hold control pin. Routing the feedback trace
underneath the unit, as mentioned previously, would be
acceptable if the line were kept to minimum width and
AB-060
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