PXB 4330
List of Tables
Page
Data Sheet
7
09.99
Table 2-1
Table 3-1
Table 4-1
Table 5-1
Table 5-2
Table 5-3
Table 5-4
Table 6-1
Table 6-2
Table 6-4
Table 6-3
Table 6-6
Table 6-5
Table 6-7
Table 6-8
Table 6-9
Table 6-10
Table 6-11
Table 6-12
Table 6-13
Table 6-14
Table 6-15
Table 6-16
Table 6-17
Table 6-18
Table 7-1
Table 7-2
Table 7-3
Table 7-4
Table 7-5
Table 7-6
Table 7-7
Table 7-8
Table 7-9
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
Guaranteed Rates for each Traffic Class. . . . . . . . . . . . . . . . . . . . . 3-42
Number of Possible Connections per PHY . . . . . . . . . . . . . . . . . . . 4-57
Standardized UTOPIA Cell Format (16-bit) . . . . . . . . . . . . . . . . . . . 5-64
Proprietary UTOPIA Cell Format (16-bit). . . . . . . . . . . . . . . . . . . . . 5-64
UTOPIA Polling Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67
External RAMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68
ABM Registers Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-75
UBMTH/DBMTH Threshold Values . . . . . . . . . . . . . . . . . . . . . . . . . 6-84
WAR Register Mapping for LCI Table Access . . . . . . . . . . . . . . . . 6-89
Registers for LCI Table Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-89
WAR Register Mapping for TCT Table Access . . . . . . . . . . . . . . . 6-93
Registers for TCT Table Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-93
Registers for Queue Configuration Table Access . . . . . . . . . . . . . 6-102
WAR Register Mapping for LCI Table Access . . . . . . . . . . . . . . . 6-103
Registers for SOT Table Access . . . . . . . . . . . . . . . . . . . . . . . . . . 6-107
WAR Register Mapping for SOT Table Access . . . . . . . . . . . . . . 6-108
Registers for QPT Upstream Table Access. . . . . . . . . . . . . . . . . . 6-123
Registers for QPT Downstream Table Access . . . . . . . . . . . . . . . 6-124
WAR Register Mapping for QPT Table Access . . . . . . . . . . . . . . 6-125
Registers SCTF Upstream Table Access . . . . . . . . . . . . . . . . . . . 6-130
Registers SCTF Downstream Table Access . . . . . . . . . . . . . . . . . 6-130
WAR Register Mapping for SCTFU/SCTFD Table access . . . . . 6-131
Registers SCTI Upstream Table Access . . . . . . . . . . . . . . . . . . . . 6-134
Registers SCTI Downstream Table Access. . . . . . . . . . . . . . . . . . 6-134
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-174
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-174
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-175
Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-177
Microprocessor Interface Write Cycle Timing (Intel) . . . . . . . . . . . 7-178
Microprocessor Interface Read Cycle Timing (Intel) . . . . . . . . . . . 7-179
Microprocessor Interface Write Cycle Timing (Motorola). . . . . . . . 7-180
Microprocessor Interface Read Cycle Timing (Motorola). . . . . . . . 7-182
Transmit Timing (16-Bit Data Bus, 50 MHz at Cell Interface,
Single PHY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-185
Receive Timing (16-Bit Data Bus, 50 MHz at Cell Interface,
Single PHY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-186
Transmit Timing (16-Bit Data Bus, 50 MHz at Cell Interface,
Multi-PHY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-186
Receive Timing (16-Bit Data Bus, 50 MHz at Cell Interface,
Multi-PHY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-187
SSRAM Interface AC Timing Characteristics. . . . . . . . . . . . . . . . . 7-189
Table 7-10
Table 7-11
Table 7-12
Table 7-13