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参数资料
| 型号： | ACD2203RS8P1 |
| 厂商： | ANADIGICS INC |
| 元件分类： | 上/下变频器 |
| 英文描述： | RF/MICROWAVE DOWN CONVERTER |
| 封装： | ROHS COMPLIANT, S8, MO-137AF, SSOP-28 |
| 文件页数： | 22/24页 |
| 文件大小： | 1607K |
| 代理商： | ACD2203RS8P1 |
PRELIMINARY DATA SHEET - Rev 1.5
04/2008
7
ACD2203
Figure 4: Serial 2-Wire Data Input Timing
Table 6: Digital 2-Wire Interface Specifications
(TA = +25 °C, VDD = +5 VDC, ref. Figure 4)
Notes:
(1) Cb is the total capacitance of one bus line in pF.
(2) For maximum 0.8 V level during Acknowledge Pulse.
3. All timing values are referred to minimum VH and maximum VL levels.
PARAMETER
SYMBOL
MIN
MAX
UNIT
CLKFrequency
fCLK
1
400
kHz
LogicHighInput(pins11,12)
VH
2.0
-
V
LogicLowInput(pins11,12)
VL
-
0.8
V
LogicInputCurrentConsumption
(pins11,12)
ILOG
-
10
A
AddressSelectInputCurrent
Consumption(pin10)
IAS
-
10
A
DataSinkCurrent(2)
IAK
-
4.0
mA
BusFreeTimebetweenaSTOPand
STARTCondition
tBUF
1.3
-
s
HoldTime(repeated)STARTCondition.
Afterthisperiod,thefirstclockpulseis
generated.
tHD;STA
0.6
-
s
LOWperiodofCLK
tLOW
1.3
-
s
HIGHperiodofCLK
tHIGH
0.6
-
s
Set-upTimeforaRepeatedSTART
Condition
tSU;STA
0.6
-
s
DataHoldTime(for2-wirebusdevices)
tHD;DAT
0.0
0.9
s
DataSet-upTime
tSU;DAT
100
-
ns
RiseTimeofDATAandCLKSignals
tR
20+0.1Cb(1)
300
ns
FallTimeofDataandCLKSignals
tF
20+0.1Cb (1)
300
ns
Set-upTimeforSTOPCondition
tSU;STO
0.6
-
s
CapacitiveLoadforEachBusLine
Cb
-
400
pF
DATA
CLK
tF
tLOW
tR
S
tHD;STA tHD;DAT
tSU;DAT
tHIGH
tF
tSU;STA
Sr
S
P
tHD;STA
tSP
tR
tBUF
tSU;STO
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