参数资料
型号: ACE1101L
厂商: Fairchild Semiconductor Corporation
英文描述: Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
中文描述: 算术控制器引擎(ACEx⑩)的低功耗应用
文件页数: 30/33页
文件大小: 152K
代理商: ACE1101L
30
www.fairchildsemi.com
ACE1101 Rev. C.8
A
11.0 Low battery detect circuit
The Low Battery Detect (LBD) circuit sets the LBD bit in the LBD
register (see Figure 24) when V
drops below the selected
threshold voltage. The threshold voltage can be adjusted from
2.4V to 3.0V
±
10% using the three most significant bits of the LBD
register. The LBDEN (Low Battery Detect enable) bit in the
initialization register is used to enable or disable the low battery
detection.
The LBD bit is read only. If 0, it indicates that the V
CC
level is higher
than the desired threshold. If set to 1, it indicates that the V
CC
level
is below the desired threshold.
The LBD circuit is disabled during HALT mode. On exiting HALT
mode, the software must wait 10
μ
s before reading the LBD bit to
ensure that the circuit has stabilized.
Voltage
Range
Bat_trim2 Bat_trim1 Bat_trim0
0
0
0
2.9 - 3.0
0
0
1
2.8 - 2.9
0
1
0
2.7 - 2.8
0
1
1
2.6 - 2.7
1
0
0
2.5 - 2.6
1
0
1
2.4 - 2.5
12.0 Brown-out detection circuit
The Brown-out detect circuit is used to reset the device when Vcc
falls below a 2.0V threshold. Once V
CC
rises above the 2.0V
threshold, a reset sequence will be generated. The Brown-out
Reset enable (BOREN) bit in the initialization register is used to
enable or disable the brown-out detection. This bit must be set
after the device has been programmed.
Brown-out is not supported on 2.2/2.7V devices.
13.0 RESET block
When a RESET sequence is initiated, all I/O registers will be reset,
setting all I/Os to high impedence inputs. The system clock is
restarted after the required clock start-up delay. A reset is gener-
ated by any one of the following three conditions:
I
Power-on RESET (as described in Section 14)
I
Brown-out RESET (as described in Section 12)
I
Watchdog RESET (as described in Section 7)
14.0 Power-on Reset
The Power-on RESET circuit is guaranteed to work if the rate of
rise of V
DD
is no slower than 10ms/1 volt. It is also necessary that
V
DD
starts from 0V.
15.0 CLOCK
The ACE1101 has an on-board oscillator trimmed to a frequency
of 2MHz, yielding a 1MHz frequency and a tolerance over tem-
perature, voltage, and device of
±
10%. Upon power-up, the on-
chip oscillator runs continuously unless entering HALT mode.
If required, an external oscillator circuit may be used depending on
the states of the CMODE bits. (See Table 14.) When the device is
driven using an external clock, the clock input to the device (G1/
CKI) can range between DC to 4MHz. For crystal configuration,
the output clock (CKO) is on the G0 pin. If an external crystal or
external RC is used, it will be internally divided by four (input
frequency/4) to yield an instruction clock cycle time of the corre-
sponding input frequency. If the device is configured for an
external square clock, it will not be divided. See Figure 26.
Table 14: CMODEx Bit Definition
CMODE1
CMODE0
Clock Type
0
0
Internal 1 MHz clock
0
1
External square clock
1
0
External crystal/resonator
1
1
External RC clock
Figure 24: LBD Register Definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bat_trim2
Bat_trim1
Bat_trim0
undefined
undefined
Undefined
undefined
LBD
Figure 25: HALT Register Definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
undefined
undefined
undefined
undefined
undefined
undefined
EIDLE
EHALT
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ACE1101LEMT8X 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
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ACE1101LMT8 功能描述:8位微控制器 -MCU TSSOP-8 1.8V-5.5V RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT