参数资料
型号: ACE1202EM
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: 微控制器/微处理器
英文描述: Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
中文描述: 8-BIT, EEPROM, 1 MHz, MICROCONTROLLER, PDSO14
封装: PLASTIC, SOIC-14
文件页数: 26/39页
文件大小: 2121K
代理商: ACE1202EM
26
www.fairchildsemi.com
ACE1202 Product Family Rev. B.1
A
After the HBC has started, software must then poll the OCFLAG
for a high pulse and restore the DAT0 register and the START
signal to continue with the next data transmission.
LOOP_HI:
IFBIT OCFLAG, HBCNTRL
JP
NXT_FRAME
JP
LOOP_HI
; Wait for OCFLAG = 1
NXT_FRAME:
LD
SBIT START, HBCNTRL
DAT0, #092H
; DAT0 = 0x92
; START / STOP = 1
If software is to proceed with another data transmission, the
OCFLAG must be zero before polling for the next OCFLAG high
pulse. However, since the specification in the example requires no
other data transmission software can proceed as desired.
LOOP_LO:
IFBIT OCFLAG, HBCNTRL
JP
LOOP_LO
Etc.
; Wait for OCFLAG = 0
; Program proceeds as desired
PSCALE
LPATTERN
HPATTERN
Down
Counter
DAT0
IR/RF
CLOCK
3
3
3
3
FRAME[2:0]
[HBCNTRL]
BPL[2:0]
[BPSEL]
BPH[2:0]
[BPSEL]
b7
ShiftCLK
NoShift
RFCLK
RFCLK
StopShift
StopShift
b7
b7
A
B
Y
A
B
Y
Fixed
Clock Divider
by 4
8
G2
G5
IOSEL
HBCNTRL[6]
[PSCALE]
CPU
CLOCK
OCFLAG
OCFLAG
HBCNTRL[7]
Sync
LOGIC
START/STOP
HBCNTRL[5]
TXBUSY
HBCNTRL[4]
Figure 21: Hardware Bit-Coder (HBC) Block Diagram
Figure 22: Bit Period Configuration (BPSEL) Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
BPL[2:0]
BPH[2:0]
Figure 23: HBC Control (HBCNTRL) Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OCFLAG
IOSEL
START/STOP
TXBUSY
0
FRAME[2:0]
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