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参数资料
| 型号： | ACS716KLATR-6BB-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 16/22页 |
| 文件大小： | 0K |
| 描述： | IC CURRENT SENSOR 120KHZ 16SOIC |
| 标准包装： | 1 |
| 灵敏度： | 100mV/A |
| 电流 - 电源： | 9mA |
| 传感器类型： | 霍尔效应 |
| 电源电压： | 3 V ~ 3.6 V |
| 输出： | 模拟，比率 |
| 响应时间： | 4µs |
| 电极标记： | 双向 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 包装： | 标准包装 |
| 其它名称： | 620-1445-6 |
ACS716
120 kHz Bandwidth, High Voltage Isolation
Current Sensor with Integrated Overcurrent Detection
Functional Description (Latching Versions)
(1)
C OC ( V CC – 2 V )
Overcurrent Fault Operation
The primary concern with high-speed fault detection is that noise
may cause false tripping. Various applications have or need to
be able to ignore certain faults that are due to switching noise or
other parasitic phenomena, which are application dependant. The
problem with simply trying to filter out this noise in the main
signal path is that in high-speed applications, with asymmetric
noise, the act of filtering introduces an error into the measure-
ment. To get around this issue, and allow the user to prevent the
fault signal from being latched by noise, a circuit was designed to
slew the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ pin voltage based on the value of the capacitor
from that pin to ground. Once the voltage on the pin falls below
2 V, as established by an internal reference, the fault output is
latched and pulled to ground quickly with an internal N-channel
MOSFET.
Fault Walk-through
The following walk-through references various sections and
attributes in the figure below. This figure shows different
fault set/reset scenarios and how they relate to the voltages on
the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ pin, FAULT_EN pin, and the internal Overcurrent
(OC) Fault node, which is invisible to the customer.
1. Because the device is enabled (FAULT_EN is high for a
minimum period of time, the Fault Enable Delay, t FED , 15 μ s
typical) and there is an OC fault condition, the device ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ
pin starts discharging.
ˉ
2. When the F Aˉ Uˉ Lˉ Tˉ pin voltage reaches approximately 2 V, the
fault is latched, and an internal NMOS device pulls the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ
pin voltage to approximately 0 V. The rate at which the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ
pin slews downward (see [4] in the figure) is dependent on the
external capacitor, C OC , on the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ pin.
ˉ
3. When the FAULT_EN pin is brought low, the F Aˉ Uˉ Lˉ Tˉ
pin starts resetting if no OC fault condition exists, and if
FAULT_EN is low for a time period greater than t OCH . The
internal NMOS pull-down turns off and an internal PMOS pull-
up turns on (see [7] if the OC fault condition still exists).
4. The slope, and thus the delay to latch the fault is controlled by
the capacitor, C OC , placed on the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ pin to ground. Dur-
ing this portion of the fault (when the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ pin is between
V CC and 2 V), there is a 3 mA constant current sink, which
discharges C OC . The length of the fault delay, t, is equal to :
t =
3 mA
where V CC is the device power supply voltage in volts, t is in
seconds and C OC is in Farads. This formula is valid for R PU
equal to or greater than 330 k Ω . For lower-value resistors,
the current flowing through the R PU resistor during a fault
event, I PU , will be larger. Therefore, the current discharging
the capacitor would be 3 mA – I PU and equation 1 may not be
valid.
ˉ
5. The F Aˉ Uˉ Lˉ Tˉ pin did not reach the 2 V latch point before the
OC fault condition cleared. Because of this, the fixed 3 mA
current sink turns off, and the internal PMOS pull-up turns on
to recharge C OC through the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ pin.
6. This curve shows V CC charging external capacitor C OC
through the internal PMOS pull-up. The slope is determined
by C OC .
7. When the FAULT_EN pin is brought low, if the fault condition
still exists, the latched ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ pin will be pulled low by the
internal 3mA current source. When fault condition is removed
then the Fault pin charges as shown in step 6.
8. At this point there is a fault condition, and the part is enabled
before the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ pin can charge to V CC . This shortens the
user-set delay, so the fault is latched earlier. The new delay
time can be calculated by equation 1, after substituting the
voltage seen on the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ pin for V CC .
V CC
1
1
1
FAULT
(Output)
2V
4
2
6
t FED
4
5
6
4
2
6
8
4
2
7
3
0V
FAULT_EN
(Input)
OC Fault
Condition
(Active High)
Time
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16
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