- 您现在的位置：买卖IC网 > PDF目录364596 > ACT-5260PC-150F17T (Aeroflex Inc.) ACT5260 64-Bit Superscaler Microprocessor PDF资料下载
参数资料
| 型号： | ACT-5260PC-150F17T |
| 厂商： | Aeroflex Inc. |
| 英文描述： | ACT5260 64-Bit Superscaler Microprocessor |
| 中文描述： | ACT5260 64位微处理器Superscaler |
| 文件页数： | 2/8页 |
| 文件大小： | 119K |
| 代理商： | ACT-5260PC-150F17T |
Aeroflex Circuit Technology
SCD5260 REV A 3/29/99 Plainview NY (516) 694-6700
2
DESCRIPTION:
The ACT5260 is a highly integrated superscalar
microprocessor that implements a superset of the
MIPS IV Instruction Set Architecture(ISA). It has a
high performance 64-bit integer unit, a high
throughput, fully pipelined 64-bit floating point unit,
an operating system friendly memory management
unit with a 48-entry fully associative TLB, a 16 KByte
2-way set associative instruction cache, a 16 KByte
2-way
set
associative
high-performance 64-bit system interface. The
ACT5260 can issue both an integer and a floating
point instruction in the same cycle.
The ACT5260 is ideally suited for high-end
embedded
control
applications
internetworking,
high
manipulation, high speed printing, and 3-D
visualization.
data
cache,
and
a
such
as
performance
image
HARDWARE OVERVIEW
The ACT5260 offers a high-level of integration
targeted
at
high-performance
applications. Some of the key elements of the
ACT5260 are briefly described below.
embedded
Superscalar Dispatch
The ACT5260 has an efficient asymmetric
superscalar dispatch unit which allows it to issue an
integer instruction and a floating-point computation
instruction
simultaneously.
superscalar issue, integer instructions include alu,
branch, load/store, and floating-point load/store,
while floating-point computation instructions include
floating-point add, subtract, combined multiply-add,
converts, etc. In combination with its high throughput
fully pipelined floating-point execution unit, the
superscalar capability of the ACT5260 provides
unparalleled price/performance in computationally
intensive embedded applications.
With
respect
to
CPU Registers
Like all MIPS ISA processors, the ACT5260 CPU
has a simple, clean user visible state consisting of 32
general purpose registers, two special purpose
registers for integer multiplication and division, a
program counter, and no condition code bits.
Pipeline
For integer operations, loads, stores, and other
non-floating-point operations, the ACT5260 uses the
simple 5-stage pipeline also found in the circuits
R4600, R4700, and R5000. In addition to this
standard pipeline, the ACT5260 uses an extended
seven stage pipeline for floating-point operations.
Like the R5000, the ACT5260 does virtual to physical
translation in parallel with cache access.
Integer Unit
Like the R5000, the ACT5260 implements the
MIPS IV Instruction Set Architecture, and is therefore
fully upward compatible with applications that run on
processors implementing the earlier generation
MIPS I-III instruction sets. Additionally, the ACT5260
includes two implementation specific instructions not
found in the baseline MIPS IV ISA but that are useful
in the embedded market place. Described in detail in
the QED RM5260 datasheet, these instructions are
integer multiply-accumulate and 3-operand integer
multiply.
The ACT5260 integer unit includes thirty-two
general purpose 64-bit registers, a load/store
architecture with single cycle ALU operations (add,
sub, logical, shift) and an autonomous multiply/divide
unit. Additional register resources include: the HI/LO
result registers for the two-operand integer multiply/
divide operations, and the program counter(PC).
Register File
The ACT5260 has thirty-two general purpose
registers with register location 0 hard wired to zero.
These registers are used for scalar integer
operations and address calculation. The register file
has two read ports and one write port and is fully
bypassed to minimize operation latency in the
pipeline.
ALU
The ACT5260 ALU consists of the integer adder/
subtractor, the logic unit, and the shifter. The adder
performs address calculations in addition to
arithmetic operations, the logic unit performs all
logical and zero shift data moves, and the shifter
performs shifts and store alignment operations. Each
of these units is optimized to perform all operations in
a single processor cycle
For additional Detail Information regarding the
operation of the Quantum Effect Design (QED)
RISCMark
RM5260
,
Microprocessor see the latest QED datasheet
(Revision 1.1 July 1998).
64-Bit
Superscalar
相关PDF资料 |
PDF描述 |
|---|---|
| ACT-5260PC-200F17T | ACT5260 64-Bit Superscaler Microprocessor |
| ACT-5260PC-100F17C | ACT5260 64-Bit Superscaler Microprocessor |
| ACT-5260PC-100F24C | ACT5260 64-Bit Superscaler Microprocessor |
| ACT-5260PC-100F24I | ACT5260 64-Bit Superscaler Microprocessor |
| ACT-5260PC-100F24M | ACT5260 64-Bit Superscaler Microprocessor |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ACT-5260PC-150F24C | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:ACT5260 64-Bit Superscaler Microprocessor |
| ACT-5260PC-150F24I | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:ACT5260 64-Bit Superscaler Microprocessor |
| ACT-5260PC-150F24M | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:ACT5260 64-Bit Superscaler Microprocessor |
| ACT-5260PC-150F24Q | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:ACT5260 64-Bit Superscaler Microprocessor |
| ACT-5260PC-150F24T | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:ACT5260 64-Bit Superscaler Microprocessor |
发布紧急采购，3分钟左右您将得到回复。