参数资料
型号: AD1377KD
厂商: Analog Devices Inc
文件页数: 2/12页
文件大小: 0K
描述: IC ADC SNGL 16BIT 32-CDIP
标准包装: 1
位数: 16
采样率(每秒): 111k
数据接口: 并联
转换器数目: 1
功率耗散(最大): 800mW
电压电源: 双 ±
工作温度: 0°C ~ 70°C
安装类型: 通孔
封装/外壳: 32-DIP(0.900",22.86mm)
供应商设备封装: 32-BBDIP-H
包装: 管件
输入数目和类型: 16 个单端,双极;16 个单端,单极
AD1376/AD1377
Rev. D | Page 10 of 12
HIGH RESOLUTION DATA ACQUISITION SYSTEM
The essential details of a high resolution data acquisition system
using a 16-bit sample-and-hold amplifier (SHA) and the
AD1376/AD1377 are shown in Figure 14. Conversion is
initiated by the falling edge of the CONVERT START pulse.
This edge drives the device’s STATUS line high. The inverter
then drives the SHA into hold mode. STATUS remains high
throughout the conversion and returns low once the conversion
is completed. This allows the SHA to re-enter track mode.
This circuit can exhibit nonlinearities arising from transients
produced at the ADC’s input by the falling edge of CONVERT
START. This edge resets the ADC’s internal DAC; the resulting
transient depends on the SHA’s present output voltage and the
ADC’s prior conversion result. In the circuit of Figure 15, the
falling edge of CONVERT START also places the SHA into hold
mode (via the ADC’s STATUS output), causing the reset
transient to occur at the same moment as the SHA’s track-and-
hold transition. Timing skews and capacitive coupling can cause
some of the transient signal to add to the signal being acquired
by the SHA, introducing nonlinearity.
00
69
9-
01
4
SHA
AD1376/
AD1377
30
21
28
22
24
27
26
19
18
31
BITS
1–16
+
CONVERT
START
–10V TO +10V
+
10
F
+
10
F
10
F
+15V
–15V
+5V
ANALOG
INPUT
–10V TO +10V
Figure 14. Basic Data Acquisition System Interconnections 16-Bit SHA
A much safer approach is to add a flip-flop, as shown in
Figure 15. The rising edge of CONVERT START places the
track-and-hold device into hold mode before the ADC reset
transients begin. The falling edge of STATUS places the SHA
back into track mode. System throughput will be reduced if a
long CONVERT START pulse is used. Throughput can be
calculated from
CS
CONV
ACQ
T
Throughput
+
=
1
where:
TACQ is the track-and-hold acquisition time.
TCONV is the time required for the ADC conversion.
TCS is the duration of CONVERT START.
The combination of the AD1376 and a 16-bit SHA can provide
greater than 50 kHz throughput. No significant track-and-hold
droop error will be introduced, provided the width of
CONVERT START is small compared with the ADC’s
conversion time.
0
06
99
-0
15
SHA
AD1376/
AD1377
30
21
28
22
24
27
26
19
18
31
BITS
1–16
+
–10V TO +10V
+
10
F
+
10
F
10
F
+15V
–15V
+5V
ANALOG
INPUT
–10V TO +10V
CONVERT
START
HC112
S
R
Q
J
Q
K
+5V
Figure 15. Improved Data Acquisition System
1
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