参数资料
型号: AD1835AASZ-REEL
厂商: Analog Devices Inc
文件页数: 4/24页
文件大小: 0K
描述: IC CODEC 2ADC/8DAC 24BIT 52MQFP
标准包装: 800
类型: 立体声音频
数据接口: 串行
分辨率(位): 24 b
ADC / DAC 数量: 2 / 8
三角积分调变:
S/N 比,标准 ADC / DAC (db): 105 / 108
动态范围,标准 ADC / DAC (db): 105 / 108
电压 - 电源,模拟: 4.5 V ~ 5.5 V
电压 - 电源,数字: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 52-QFP
供应商设备封装: 52-MQFP(10x10)
包装: 带卷 (TR)
REV. A
–12–
AD1835A
DAC ENGINE
CLOCK SCALING
1
2
2/3
MCLK
DAC I/P
INTERPOLATION
FILTER
Σ-
MODULATOR
DAC
48kHz/96kHz/192kHz
ADC ENGINE
ADC O/P
OPTIONAL
HPF
DECIMATOR /
FILTER
48kHz/96kHz
ANALOG
OUTPUT
ANALOG
INPUT
12.288MHz
IMCLK = 24.576MHz
Σ-
MODULATOR
Figure 2. Modulator Clocking Scheme
CLATCH
CCLK
CIN
COUT
D0
D8
D0
D15
D14
D9
D8
t
CCH tCCL
D9
t
CDS tCDH
t
CLS
t
CLH
t
COD
t
COTS
t
CCP
t
COE
Figure 3. Format of SPI Timing
Table III. ADC Sample Rate Settings
Sample Rate
ADC Control 1 Register
IMCLK/512
1100000xx0xxxxxx (48 kHz)
IMCLK/256
1100000xx1xxxxxx (96 kHz)
To maintain the highest performance possible, the clock jitter of
the master clock signal should be limited to less than 300 ps
rms, measured using the edge-to-edge technique. Even at these
levels, extra noise or tones may appear in the DAC outputs if
the jitter spectrum contains large spectral peaks. It is highly
recommended that the master clock be generated by an inde-
pendent crystal oscillator. In addition, it is especially important
that the clock signal not be passed through an FPGA or other
large digital chip before being applied to the AD1835A. In most
cases, this will induce clock jitter due to the fact that the clock
signal is sharing common power and ground connections with
unrelated digital output signals.
RESET and Power-Down
PD/RST will power down the chip and set the control registers
to their default settings. After
PD/RST is de-asserted, an
initialization routine will run inside the AD1835A to clear all
memories to zero. This initialization lasts approximately 20
LRCLK intervals. During this time, it is recommended that no
SPI writes occur.
Power Supply and Voltage Reference
The AD1835A is designed for 5 V supplies. Separate power supply
pins are provided for the analog and digital sections. These pins
should be bypassed with 100 nF ceramic chip capacitors, as
close to the pins as possible, to minimize noise pickup. A bulk
aluminum electrolytic capacitor of at least 22 F should also be
provided on the same PC board as the codec. For critical applica-
tions, improved performance will be obtained with separate
supplies for the analog and digital sections. If this is not pos-
sible, it is recommended that the analog and digital supplies be
isolated by two ferrite beads in series with the bypass capacitor
of each supply. It is important that the analog supply be as clean
as possible.
The internal voltage reference is brought out on the FILTR pin
and should be bypassed as close as possible to the chip, with a
parallel combination of 10
F and 100 nF. The reference volt-
age may be used to bias external op amps to the common-mode
voltage of the analog input and output signal pins. The current
drawn from the VREF pin should be limited to less than 50 A.
Serial Control Port
The AD1835A has an SPI compatible control port to permit
programming the internal control registers for the ADCs and
DACs and for reading the ADC signal levels from the internal
peak detectors. The SPI control port is a 4-wire serial control port.
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