参数资料
型号: AD1836AASZ
厂商: Analog Devices Inc
文件页数: 11/24页
文件大小: 0K
描述: IC CODEC 4ADC/6DAC 24 BIT 52MQFP
产品培训模块: Interfacing AV Converters to Blackfin Processors
标准包装: 1
类型: 通用
数据接口: 串行
分辨率(位): 24 b
ADC / DAC 数量: 4 / 6
三角积分调变:
S/N 比,标准 ADC / DAC (db): 105 / 108
动态范围,标准 ADC / DAC (db): 105 / 108
电压 - 电源,模拟: 4.75 V ~ 5.25 V
电压 - 电源,数字: 4.75 V ~ 5.25 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 52-QFP
供应商设备封装: 52-MQFP(10x10)
包装: 托盘
产品目录页面: 776 (CN2011-ZH PDF)
配用: AD1836AZ-DBRD-ND - BOARD EVAL FOR AD1836A
Data Sheet
AD1836A
Rev. A | Page 19 of 24
SPI CONTROL REGISTERS
Note that all control registers default to zero at power-up.
Table 12. Serial SPI Word Format
Register Address
Read/Write
Reserved
Data Field
15:12
11
10
9:0
4 Bits
1 = Read
0 = Write
0
10 Bits
Table 13. Register Addresses and Functions
Register Address
RD/WR
Reserved
Function
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bits 9:0
0
DAC Control 1
0
1
0
DAC Control 2
0
1
0
DAC1L Volume
0
1
0
DAC1R Volume
0
1
0
DAC2L Volume
0
1
0
1
0
DAC2R Volume
0
1
0
DAC3L Volume
0
1
0
DAC3R Volume
1
0
ADC1L—Peak Level (Read-Only)
1
0
1
0
ADC1R—Peak Level (Read-Only)
1
0
1
0
ADC2L—Peak Level (Read-Only)
1
0
1
0
ADC2R—Peak Level (Read-Only)
1
0
ADC Control 1
1
0
1
0
ADC Control 2
1
0
ADC Control 3
1
0
Reserved
Table 14. DAC Control Register 1
Packed Mode: Eight channels are “packed” in DSDATA1 serial input. Packed Mode 128: Refer to Figure 7. Packed Mode 256: Refer to Figure 8.
Address
RD/WR
Reserved
Function
De-emphasis
Serial Mode
Data-Word
Width
Power-Down
Interpolator
Mode
Reserved
15, 14, 13, 12
11
10
9, 8
7, 6, 5
4, 3
2
1
0
0000
0
00 = None
01 = 44.1 kHz
10 = 32.0 kHz
11 = 48.0 kHz
000 = I2S
001 = RJ
010 = DSP
011 = LJ
100 = Packed Mode 256
101 = Packed Mode 128
110 = Reserved
111 = Reserved
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = Reserved
0 = Normal
1 = PWRDWN
0 = 8× (48 kHz)
1 = 4× (96 kHz)
0
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