参数资料
| 型号： | AD1854JRSZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/12页 |
| 文件大小： | 0K |
| 描述： | IC DAC STEREO 96KHZ 5V 28SSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1,500 |
| 位数： | 20 |
| 数据接口： | DSP，I²S，串行 |
| 转换器数目： | 2 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 250mW |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 28-SSOP |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 4 电压，单极 |
| 采样率（每秒）： | 96k |
AD1854
–7–
REV. A
MSB–2
MSB–1
LSB+2
LSB+1
LSB
MSB–2
MSB–1
MSB
LSB+2
LSB+1
LSB
MSB–1
MSB
L/
RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
LEFT CHANNEL
RIGHT CHANNEL
MSB
Figure 3. Left-Justified Mode
L/
RCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
LSB
MSB–1
MSB–2
LSB+2
LSB+1
LSB
MSB
MSB–1
MSB–2
LSB+2
LSB+1
LSB
MSB
MSB–1
MSB
Figure 4. 32
× FS Packed Mode
D15
D14
D0
tCHD
tCCH
tCSU
tCCL
tCLL
tCLH
CDATA
CCLK
CLATCH
tCCP
Figure 5. Serial Control Port Timing
Serial Control Port
The AD1854 serial control port is SPI-compatible. SPI (Serial
Peripheral Interface) is an industry standard serial port protocol.
The write-only serial control port gives the user access to: select
input mode, soft power-down control, soft de-emphasis, channel-
specic attenuation and mute (both channels at once). The
AD1854 serial control port consists of three signals, control
clock CCLK (Pin 4), control data CDATA (Pin 5), and control
latch CLATCH (Pin 3). The control data input must be valid
on the control clock rising edge, and the control clock must make a
LO to HI transition when there is valid data. The control latch
must make a LO-to-HI transition after the LSB has been clocked
into the AD1854, while the control clock is inactive. The timing
relation between these signals is shown in Figure 5. The control
bits are assigned as in Table IV.
Table III. Digital Timing
Min
Unit
tCCH
CCLK HI Pulsewidth
40 (Burst Mode)
ns
tCCL
CCLK LO Pulsewidth
40 (Burst Mode)
ns
tCCP
CCLK Period
80 (Burst Mode)
ns
tCSU
CDATA Setup Time
10
ns
tCHD CDATA Hold Time
10
ns
tCLL
CLATCH LO Pulsewidth
10
ns
tCLH
CLATCH HI Pulsewidth
130 (Burst Mode)
ns
The serial control port is byte oriented. The data is MSB rst,
and is unsigned. There is one control register for the left
channel or the right channel, as distinguished by Bit Data 10.
For power-up and reset, the default settings are: Data 11 the
mute control bit, reset default state is LO, which is the normal
(nonmuted) setting. Data 10 is LO, the Volume 9 through
Volume 0 control bits have a reset default value of 11 1111 1111,
which is an attenuation of 0.0 dB (i.e., full scale, no attenuation).
The intent with these reset defaults is to enable AD1854 applica-
tions without requiring the use of the serial control port. For those
users who do not use the serial control port, it is still possible to
mute the AD1854 output by using the MUTE (Pin 23) signal.
Note that the serial control port timing is asynchronous to the
serial data port timing. Changes made to the attenuator level
will be updated on the next edge of the L/RCLK after the
CLATCH write pulse as shown in Figure 8.
The SPI port can be used in either of two modes, Burst Mode,
or Continuous CCLK Mode, as described below.
Continuous CCLK Mode
In this mode, the maximum CCLK frequency is 3 MHz. The
CCLK can run continuously between transactions. Please note
that the LO-to-HI transition of the CLATCH with respect to
the rising edge of CCLK must be at least 130 ns, as shown in
Figure 6.
Table IV. Serial Control Bit Definitions
MSB
LSB
Data 15 Data 14
Data 13 Data 12
Data 11
Data 10 Data 9
Data 8
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
IDPM1
IDPM0
Soft
1/Mute
1/Right
Volume Volume
Volume
Volume Volume
Input
Power-
De-
0/Normal
0/Left
Control Control
Control
Control Control
Mode1
Mode0
Down
Emphasis (Nonmute)
Data
Select
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD1854KRS | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:STEREO,96KHZ, MULTIBIT SIGMA DELTA DAC - Bulk |
| AD1854KRSRL | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP T/R 制造商:Analog Devices 功能描述:DAC 2CH DELTA-SIGMA 24BIT 28SSOP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:STEREO,96KHZ, MULTIBIT SIGMA DELTA DAC - Tape and Reel |
| AD1855 | 制造商:AD 制造商全称:Analog Devices 功能描述:Stereo, 96 kHz, Multibit DAC |
| AD1855JRS | 制造商:Rochester Electronics LLC 功能描述:.3EREO, 96KHZ, MULTIBIT SIGMA DELTA DAC - Bulk 制造商:Analog Devices 功能描述:IC DAC MULTIBIT SIGMA DELTA 1855 |
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