参数资料
型号: AD260AND-1
厂商: Analog Devices Inc
文件页数: 6/8页
文件大小: 0K
描述: IC LOGIC ISO/1.75KV 1:4IO 22DIP
标准包装: 1
系列: IsoLogic™
输入 - 1 侧/2 侧: 1/4
通道数: 5
电源电压: 4 V ~ 5.75 V
电压 - 隔离: 1750Vrms
数据速率: 40MBd
传输延迟: 14ns
输出类型: 三态
封装/外壳: 22-DIP 模块
供应商设备封装: 22-PDIP
包装: 管件
工作温度: -25°C ~ 85°C
AD260
( Continued from pag e 1)
Integral Isolated Power: The AD260 includes an integral,
uncommitted and flexible 1 Watt power transformer for devel-
oping isolated field power sources.
Field and System Enable Functions : Both the isolated and
nonisolated sides of the AD260 have ENABLE pins that three-
state all outputs. Upon reenabling these pins, all outputs are
updated to reflect the current input logic level.
CE Certifiable : Simply by adding the external bypass capacitors
at the supply pins, the AD260 can attain CE certification in
most applications (to the EMC directive) and conformance to
the low voltage (safety) directive is assured by the EN60950
certification.
GENERAL ATTRIBUTES
The AD260 provides five HCMOS/ACMOS compatible isolated
logic lines with ≥ 10 kV/ μ s common-mode transient immunity.
The case design and pin arrangement provides greater than
18 mm spacing between field and system side conductors, pro-
viding CSA/IS and IEC creepage spacing consistent with 750 V
mains isolation.
Edge “fidelity,” or the difference in propagation time for rising
and falling edges, is typically less than ± 1 ns.
Power consumption, unlike opto-isolators, is a function of operat-
ing frequency. Each logic line barrier driver requires about 160 μ A
per MHz and each receiver 40 μ A per MHz plus, of course, 4 mA
total idle current (each side). The supply current diminishes
slightly with increasing temperature (about –0.03%/ ° C).
The total capacitance spanning the isolation barrier is less than
10 pF.
The minimum width of a pulse that can be accurately coupled
across the barrier is about 25 ns. Therefore the maximum
square-wave frequency of operation is 20 MHz.
Logic information is sent across the barrier as “set-hi/set-lo”
data that is derived from logic level transitions of the input. At
power-up or after a fault condition, an output might not repre-
sent the state of the respective channel input to the isolator. An
internal circuit operates in the background which interrogates all
inputs about every 5 μ s and in the absence of logic transitions,
sends appropriate “set-hi” or “set-lo” data across the barrier.
Recovery time from a fault condition or at power-up is thus
between 5 μ s and 10 μ s.
The five unidirectional logic lines have six possible combina-
tions of “ins” and “outs,” or transmitter/receiver pairs; hence
SCHMITT
DATA
3.5kV
ISOLATION
DATA
OUTPUT
there are six AD260 part configurations (see Table I).
Each 20 MHz logic line has a Schmidt trigger input and a three-
DATA IN
TRIGGER
TRANSMITTER
D Q
BARRIER
RECEIVER BUFFER
OUT
state output (on the other side of the isolation barrier) and 14 ns of
propagation delay. A single enable pin on either side of the
barrier causes all outputs on that side to go three-state and all
ENABLE
G
GATED
CONTINUOUS
UPDATE CIRCUIT
ENABLE
inputs (driven pins) to ignore their inputs and retain their last
known state.
Note: All unused logic inputs (1–5) should be tied either high or low,
TRANSPARENT
LATCH
Figure 1. Simplified Block Diagram
but not left floating.
PROPAGATION DELAY
POSITIVE GOING
INPUT THRESHOLD
INPUT
OUTPUT
+3V
+2V
63%
NEGATIVE GOING
INPUT THRESHOLD
HYSTERESIS
37%
t PD
t PLH
t PD
t PHL
t ff
EFFECTIVE CIRCUIT MODEL FOR ONE ISOLATED LOGIC LINE
SCHMITT
TRIGGER
DELAY LINE
BUFFER
5pF
INPUT
CAPACITANCE
12.5ns
t PD
t rr = t ff = 100 x C TOTAL OUTPUT CAPACITANCE
100
5pF
OUTPUT
CAPACITANCE
0.5ns – NO LOAD
= 5.5ns INTO 50pF
TOTAL DELAY = ( t PLH OR t PHL ) = t PD + ( t rr OR t ff )
13ns (NO LOAD), 18ns (50pF LOAD)
Figure 2. Typical Timing and Delay Models
–6 –
REV. 0
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AD260ANDS-5 制造商:Rochester Electronics LLC 功能描述:- Bulk