参数资料
型号: AD261BND-5
厂商: Analog Devices Inc
文件页数: 5/6页
文件大小: 0K
描述: IC LOGIC ISO/3.5KV 5:0IO 22DIP
标准包装: 1
系列: IsoLogic™
输入 - 1 侧/2 侧: 2/3
通道数: 5
电源电压: 4 V ~ 5.75 V
电压 - 隔离: 1250Vrms
数据速率: 40MBd
传输延迟: 14ns
输出类型: 三态
封装/外壳: 22-DIP 模块
供应商设备封装: 22-PDIP
包装: 管件
工作温度: -25°C ~ 85°C
AD261
AD261 CONFIGURATIONS
AD261-4
AD261-5
STA EE-
THR ATE
F0
THR
TE
LINE 0
LATCH
D
E
S0
F0
LATCH
D
E
LINE 0
EE-
ST
S0
THR ATE
THR ATE
THR ATE
THR ATE
THR ATE
THR ATE
THR ATE
THR ATE
F1
F2
F3
F4
LATCH
D
E
LATCH
D
E
LATCH
D
E
LATCH
D
E
LINE 1
LINE 2
LINE 3
LINE 4
EE-
ST
EE-
ST
EE-
ST
EE-
ST
2
3
4
5
S1
S2
S3
S4
F1
F2
F3
F4
LATCH
D
E
LATCH
D
E
LATCH
D
E
LATCH
D
E
LINE 1
LINE 2
LINE 3
LINE 4
EE-
ST
EE-
ST
EE-
ST
EE-
ST
2
3
4
5
S1
S2
S3
S4
ENABLE FLD 17
6
ENABLE SYS
ENABLE FLD 17
6
ENABLE SYS
+5V dc FLD 16
5V RTN FLD 15
+5V dc
5V dc RTN
+5V dc
5V dc RTN
7
8
+5V dc SYS
5V RTN SYS
+5V dc FLD 16
5V RTN FLD 15
+5V dc
5V dc RTN
+5V dc
5V dc RTN
7
8
+5V dc SYS
5V RTN SYS
FIELD
SYSTEM
FIELD
SYSTEM
( Continued from pag e 1)
Field and System Enable Functions : Both the isolated and
nonisolated sides of the AD261 have ENABLE pins that three-
state all outputs. Upon reenabling these pins, all outputs are
updated to reflect the current input logic level.
CE Certifiable : Simply by adding the external bypass capacitors
at the supply pins, the AD261 can attain CE certification in
most applications (to the EMC directive) and conformance to
the low voltage (safety) directive is assured by the EN60950
certification.
Table I. Model Number and Pinout Function
GENERAL ATTRIBUTES
The AD261 provides five HCMOS compatible isolated logic
lines with ≥ 10 kV/ μ s common-mode transient immunity.
The case design and pin arrangement provides greater than
18 mm spacing between field and system side conductors, pro-
viding CSA/IS and IEC creepage spacing consistent with 750 V
mains isolation.
The five unidirectional logic lines have six possible combina-
tions of “ins” and “outs,” or transmitter/receiver pairs; hence
there are six AD261 part configurations (see Table I).
Each 20 MHz logic line has a Schmidt trigger input and a three-
state output (on the other side of the isolation barrier) and 14 ns of
propagation delay. A single enable pin on either side of the
Pin
AD261-0
AD261-1 AD261-2 AD261-3 AD261-4 AD261-5
barrier causes all outputs on that side to go three-state and all
1
2
3
4
5
6
7
8
9–14
15
16
17
18
19
20
21
22
S0 (Xmt)
S1 (Xmt)
S2 (Xmt)
S3 (Xmt)
S4 (Xmt)
ENABLE SYS
+5 V dc SYS
5 V RTN SYS
5 V RTN FLD
+5 V dc FLD
ENABLE FLD
F0 (Rcv)
F1 (Rcv)
F2 (Rcv)
F3 (Rcv)
F4 (Rcv)
S0 (Xmt)
S1 (Xmt)
S2 (Xmt)
S3 (Xmt)
S4 (Rcv)
*
*
*
*
*
*
F0 (Rcv)
F1 (Rcv)
F2 (Rcv)
F3 (Rcv)
F4 (Xmt)
S0 (Xmt) S0 (Xmt)
S1 (Xmt) S1 (Xmt)
S2 (Xmt) S2 (Rcv)
S3 (Rcv) S3 (Rcv)
S4 (Rcv) S4 (Rcv)
* *
* *
* *
Not Present
* *
* *
* *
F0 (Rcv) F0 (Rcv)
F1 (Rcv) F1 (Rcv)
F2 (Rcv) F2 (Xmt)
F3 (Xmt) F3 (Xmt)
F4 (Xmt) F4 (Xmt)
S0 (Xmt)
S1 (Rcv)
S2 (Rcv)
S3 (Rcv)
S4 (Rcv)
*
*
*
*
*
F0 (Rcv)
F1 (Xmt)
F2 (Xmt)
F3 (Xmt)
F4 (Xmt)
S0 (Rcv)
S1 (Rcv)
S2 (Rcv)
S3 (Rcv)
S4 (Rcv)
*
*
*
*
*
*
F0 (Xmt)
F1 (Xmt)
F2 (Xmt)
F3 (Xmt)
F4 (Xmt)
inputs (driven pins) to ignore their inputs and retain their last
known state.
Note: All unused logic inputs (1–5) should be tied either high or low,
but not left floating.
Edge “fidelity,” or the difference in propagation time for rising
and falling edges, is typically less than ± 1 ns.
Power consumption, unlike opto-isolators, is a function of operat-
ing frequency. Each logic line barrier driver requires about 160 μ A
per MHz and each receiver 40 μ A per MHz plus, of course, 4 mA
total idle current (each side). The supply current diminishes
slightly with increasing temperature (about –0.03%/ ° C).
The total capacitance spanning the isolation barrier is less than
10 pF.
The minimum period of a pulse that can be accurately coupled
across the barrier is about 25 ns. Therefore the maximum
*Pin function is the same on all models, as shown in the AD261-0 column.
REV. 0
square-wave frequency of operation is 20 MHz.
–5 –
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