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| 型号： | AD5061BRJZ-1REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/20页 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT SPI/SRL SOT23-8 |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1 |
| 系列： | nanoDAC™ |
| 设置时间： | 4µs |
| 位数： | 16 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 6mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-8 |
| 供应商设备封装： | SOT-23-8 |
| 包装： | 标准包装 |
| 输出数目和类型： | 1 电压，单极；1 电压，双极 |
| 采样率（每秒）： | 1.3M |
| 其它名称： | AD5061BRJZ-1REEL7DKR |
AD5061
Rev. B | Page 15 of 20
THEORY OF OPERATION
The AD5061 is a single 16-bit, serial input, voltage output DAC.
It operates from supply voltages of 2.7 V to 5.5 V. Data is writ-
ten to the AD5061 in a 24-bit word format, via a 3-wire serial
interface.
The AD5061 incorporates a power-on reset circuit that ensures
the DAC output powers up to zero-scale or midscale. The
device also has a software power-down mode pin that reduces
the typical current consumption to less than 1 μA.
DAC ARCHITECTURE
The DAC architecture of the AD5061 consists of two matched
DAC sections. A simplified circuit diagram is shown in
Figure 37. The four MSBs of the 16-bit data word are decoded
to drive 15 switches, E1 to E15. Each of these switches connects
one of 15 matched resistors to either DACGND or VREF
buffer
output. The remaining 12 bits of the data word drive switches
S0 to S11 of a 12-bit voltage mode R-2R ladder network.
2R
04
776
2-
0
27
S0
VREF
2R
S1
2R
S11
2R
E1
2R
E2
2R
E15
2R
VOUT
12-BIT R-2R LADDER
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
Figure 37. DAC Ladder Structure
REFERENCE BUFFER
The AD5061 operates with an external reference. The reference
input (VREF) has an input range of 2 V to VDD 50 mV. This
input voltage is then used to provide a buffered reference for the
DAC core.
SERIAL INTERFACE
The AD5061 has a 3-wire serial interface (SYNC, SCLK, and
DIN), which is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs. See
for a
timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making these parts compatible with high speed
DSPs. On the 24th falling clock edge, the last data bit is clocked
in and the programmed function is executed (that is, a change
in the DAC register contents and/or a change in the mode of
operation).
At this stage, the SYNC line may be kept low or be brought
high. In either case, it must be brought high for a minimum of
12 ns before the next write sequence so that a falling edge of
SYNC can initiate the next write sequence. Because the SYNC
buffer draws more current when VIH = 1.8 V than it does when
VIH = 0.8 V, SYNC should be idled low between write sequences
for an even lower power operation of the part. As previously
indicated, however, it must be brought high again just before
the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide; see Figure 38. PD1 and
PD0 are control bits that control which mode of operation the
part is in (normal mode or any one of three power-down
modes). There is a more complete description of the various
modes in the Power-Down Modes section. The next 16 bits are
the data bits. These are transferred to the DAC register on the
24th falling edge of SCLK.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 24 falling edges of SCLK and the DAC is updated on the
24th falling edge. However, if SYNC is brought high before the
24th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs; see
.
DATA BITS
DB15 (MSB)
DB0 (LSB)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NORMAL OPERATION
1k TO GND
100k TO GND
3-STATE
POWER-DOWN MODES
0
1
0
1
0
1
04
762-
02
8
00
0
PD1
PD0
Figure 38. Input Register Contents
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| AD5061BRJZ-2 | 制造商:Analog Devices 功能描述:DAC SGL R-2R 16BIT 8PIN SOT-23 - Bulk |
| AD5061BRJZ-2500RL7 | 功能描述:IC DAC 16BIT SPI/SRL SOT23-8 RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:nanoDAC™ 产品培训模块:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色产品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 标准包装:91 系列:- 设置时间:4µs 位数:10 数据接口:MICROWIRE?，串行，SPI? 转换器数目:8 电压电源:单电源 功率耗散（最大）:2.7mW 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:14-WFDFN 裸露焊盘 供应商设备封装:14-DFN-EP（4x3） 包装:管件 输出数目和类型:8 电压，单极 采样率（每秒）:* |
| AD5061BRJZ-2REEL7 | 功能描述:IC DAC 16BIT SPI/SRL SOT23-8 RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:nanoDAC™ 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:3,000 系列:nanoDAC™ 设置时间:80µs 位数:18 数据接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 转换器数目:1 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:SOT-23-8 供应商设备封装:SOT-23-8 包装:带卷 (TR) 输出数目和类型:1 电压，单极 采样率（每秒）:- 产品目录页面:784 (CN2011-ZH PDF) 配用:EVAL-AD5680EBZ-ND - BOARD EVAL FOR AD5680 其它名称:AD5680BRJZ-2REEL7TR |
| AD5061BRJZ-3 | 制造商:Analog Devices 功能描述:DAC SGL R-2R 16BIT 8PIN SOT-23 - Bulk |
| AD5061YRJZ-1 | 制造商:Analog Devices 功能描述:DAC SGL R-2R 16BIT 8PIN SOT-23 - Bulk |
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