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参数资料
| 型号： | AD5063BRMZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/20页 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT 2.7-5.5V 10MSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1,000 |
| 系列： | nanoDAC™ |
| 设置时间： | 4µs |
| 位数： | 16 |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 1 电压，单极；1 电压，双极 |
| 采样率（每秒）： | 333k |
AD5063
Rev. C | Page 14 of
20
POWER-ON TO MIDSCALE
The AD5063 contains a power-on reset circuit that controls the
output voltage during power-up. The DAC register is filled with
the midscale code, and the output voltage is midscale until a
valid write sequence is made to the DAC. This is useful in
applications where it is important to know the state of the DAC
output while it is in the process of powering up.
SOFTWARE RESET
The device can be put into software reset by setting all bits in
the DAC register to 1; this includes writing 1s to Bits D23 to
D16, which is not the normal mode of operation. Note that the
SYNC interrupt command cannot be performed if a software
reset command is started.
POWER-DOWN MODES
The AD5063 contains four separate modes of operation. These
modes are software-programmable by setting two bits (DB17
and DB16) in the control register. Table 6 shows how the state
of the bits corresponds to the operating mode of the device.
Table 6. Modes of Operation for the AD5063
DB17
DB16
Operating Mode
0
Normal operation
Power-down mode:
0
1
Three-state
1
0
100 kΩ to GND
1
1 kΩ to GND
When both bits are set to 0, the part has normal power con-
sumption. However, for the three power-down modes, the
supply current falls to 200 nA at 5 V (50 nA at 3 V). Not
only does the supply current fall, but the output stage is
also internally switched from the output of the amplifier to
a resistor network of known values. This has the advantage
that the output impedance of the part is known while the part
is in power-down mode. There are three options: The output
can be connected internally to GND through either a 1 kΩ
resistor or a 100 kΩ resistor, or it can be left open-circuited
(three-stated). The output stage is illustrated in Figure 29.
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
VOUT
AD5063
DAC
04
76
6-
02
9
Figure 29. Output Stage During Power-Down
The bias generator, DAC core, and other associated linear
circuitry are all shut down when the power-down mode is
activated. However, the contents of the DAC register are unaffected
when in power-down. The time to exit power-down is typically
MICROPROCESSOR INTERFACING
AD5063 to ADSP-2101/ADSP-2103 Interface
Figure 30 shows a serial interface between the AD5063 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in the SPORT transmit alternate framing
mode. The ADSP-2101/ADSP-2103 SPORT are programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, and
16-bit word length. Transmission is initiated by writing a word
to the Tx register after the SPORT has been enabled.
AD5063
1ADDITIONAL PINS OMITTED FOR CLARITY
TFS
DT
SCLK
SYNC
DIN
SCLK
04
76
6-
03
0
ADSP-2101/
ADSP-21031
Figure 30. AD5063 to ADSP-2101/ADSP-2103 Interface
0
476
6-
0
31
DB23
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 24TH FALLING EDGE
VALID WRITE SEQUENCE:
OUTPUT UPDATES ON THE 24TH FALLING EDGE
SYNC
SCLK
DIN
Figure 31. SYNC Interrupt Facility
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD5063BRMZ-REEL71 | 制造商:AD 制造商全称:Analog Devices 功能描述:Fully Accurate 16-Bit VOUT nanoDAC SPI Interface 2.7 V to 5.5 V in an MSOP |
| AD5064 | 制造商:AD 制造商全称:Analog Devices 功能描述:Industrial Current/Voltage Output Driver |
| AD50641 | 制造商:AD 制造商全称:Analog Devices 功能描述:Fully Accurate, 16-Bit, Unbuffered VOUT, Quad SPI Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP |
| AD50643-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD50647-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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