参数资料
型号: AD5100YRQZ-0
厂商: Analog Devices Inc
文件页数: 5/36页
文件大小: 0K
描述: IC VOLTAGE MONITOR
标准包装: 98
类型: 系统管理器
监视电压数目: 4
输出: 推挽式,图腾柱
复位: 低有效
复位超时: 标准为 60 µs
电压 - 阀值: 可调节/可选择
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP
包装: 管件
AD5100
Parameter
Symbol
Conditions
Min
Typ 1
Max
Unit
LOW VOLTAGE MONITORING INPUTS
V 3MON , V 4MON
V 3MON Voltage Range
V 3MON
2.0
5.5
V
Input Resistance
R IN_V3MON
85
130
180
V 3MON Threshold Tolerance
ΔV 3MON
T A = 25°C
?2.5
+2.5
%
(See Figure 10 and Table 6)
T A = ?40°C to +85°C
T A = ?40°C to +125°C
?2.75
?3
+2.75
+3
%
%
V 3MON Hysteresis
V 3_HYSTERESIS
1.2
%
V 4MON Voltage Range 4
V 4MON
0.9
30
V
Input Resistance
R IN_V4MON
500
675
860
V 4MON Threshold Tolerance
ΔV 4MON
T A = 25°C
?2.5
+2.5
%
(See Figure 12 and Table 6)
T A = ?40°C to +85°C
T A = ?40°C to +125°C
?2.75
?3
+2.75
+3
%
%
V 4MON Hysteresis
V 4_HYSTERESIS
5
%
RESET
RESET Hold Time Tolerance
Δt RS_HOLD
T A = 25°C; does not apply to
?10
+10
%
(See Figure 10 , Figure 12 , and Table 8 )
Code 0x6 and Code 0x7
T A = ?40°C to +125°C; does not
?17
+17
%
apply to Code 0x6 and Code 0x7
V 3MON /V 4MON -to-RESET Delay
t RS_DELAY
60
μs
RESET Output Voltage High
V OH
V 3MON ≥ 4.38 V, I SOURCE = 120 μA
2.7 V < V 3MON ≤ 4.38 V,
V 3MON ? 1.5
0.8 × V 3MON
V
V
I SOURCE = 30 μA
2.3 V < V 3MON ≤ 2.7 V,
I SOURCE = 20 μA
1.8 V ≤ V 3MON ≤ 2.3 V,
I SOURCE = 8 μA
0.8 × V 3MON
0.8 × V 3MON
V
V
RESET Output Voltage Low
RESET Output Short-Circuit Current 5
Glitch Immune Time
V 4OUT Maximum Output
V 4OUT Propagation Delay
V 4OUT Maximum Frequency
V OL
I SOURCE
t GLITCH
V 4OUT_MAX
t V4OUT_DELAY
f V4OUT
V 3MON > 4.38 V, I SINK = 3.2 mA
V 3MON < 4.38 V, I SINK = 1.2 mA
RESET = 0, V 3MON = 5.5 V
RESET = 0, V 3MON = 3.6 V
Open drain
Applies to RESET disabled only
50
70
10
0.4
0.3
825
400
5.5
V
V
μA
μA
μs
V
μs
kHz
WDI (WATCHDOG INPUT)
WDI Programmable Timeout Tolerance
Δt WD
T A = 25°C
?10
+10
%
(see Figure 13 and Table 8)
T A = ?40°C to +125°C
?17
+17
%
WDI Pulse Width
t WDI
50
ns
Watchdog Initiated RESET Pulse Width
Watchdog Initiated SHDN
t WDR
t WD_SHDN
When no WDI
When no WDI activity > 4 t WD
t WD /50
1
ms
sec
WDI Input Voltage Low
WDI Input Voltage High
WDI Input Current
V IL_WD
V IH_WD
WDI = V 3MON
WDI = 0
0.7 × V 3MON
?20
0.3 × V 3MON
160
V
V
μA
μA
MR (MANUAL RESET) INPUT
MR Input Voltage Low
MR Input Voltage High
Input Current
MR Pulse Width
MR Deglitching
MR-to-RESET Delay
V IL_MR
V IH_MR
t MR
t MR_GLITCH
t MR_DELAY
0.7 × V 3MON
1
100
1
0.3 × V 3MON
1
V
V
μA
μs
ns
μs
Rev. A | Page 5 of 36
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