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参数资料
| 型号： | AD5114BCPZ80-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 23/28页 |
| 文件大小： | 0K |
| 描述： | IC DGTL POT 32POS 80K SGL 8LFCSP |
| 标准包装： | 3,000 |
| 接片： | 32 |
| 电阻（欧姆）： | 80k |
| 电路数： | 1 |
| 温度系数： | 标准值 35 ppm/°C |
| 存储器类型： | 非易失 |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.8 V ~ 5 V，2.3 V ~ 5.5V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-UFDFN 裸露焊盘，CSP |
| 供应商设备封装： | 8-LFCSP-UD（2x2） |
| 包装： | 带卷 (TR) |
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AD5110/AD5112/AD5114
Data Sheet
Rev. B | Page 4 of 28
Parameter
Symbol
Test Conditions/Comments
Min
Typ1
Max
Unit
POWER SUPPLIES
Single-Supply Power Range
2.3
5.5
V
Logic Supply Range
1.8
VDD
V
Positive Supply Current
IDD
VDD = 5 V
0.75
3.5
A
VDD = 2.7 V
2.5
A
VDD = 2.3 V
2.4
A
EEMEM Store Current3, 6
IDD_NVM_STORE
2
mA
EEMEM Read Current3, 7
IDD_NVM_READ
320
A
Logic Supply Current
ILOGIC
VIH = VLOGIC or VIL = GND
30
nA
Power Dissipation8
PDISS
VIH = VLOGIC or VIL = GND
5
W
Power Supply Rejection3
PSR
VDD/VSS = 5 V ± 10%
RAB = 10 k
50
dB
RAB = 80 k
64
dB
DYNAMIC CHARACTERISTICS3, 9
Bandwidth
BW
Code = half scale, 3 dB
RAB = 10 k
2
MHz
RAB = 80 k
200
kHz
Total Harmonic Distortion
THD
VA = VDD/2 +1 V rms, VB = VDD/2,
f = 1 kHz, code = half scale
RAB = 10 k
80
dB
RAB = 80 k
85
dB
VW Settling Time
ts
VA = 5 V, VB = 0 V,
±0.5 LSB error band
RAB = 10 k
3
s
RAB = 80 k
12
s
Resistor Noise Density
eN_WB
Code = half scale, TA = 25°C,
f = 100 kHz
RAB = 10 k
9
nV/√Hz
RAB = 80 k
20
nV/√Hz
FLASH/EE MEMORY RELIABILITY3
Endurance10
TA = 25°C
1
MCycles
100
kCycles
Data Retention11
50
Years
1 Typical values represent average readings at 25°C, V
DD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.75 × VDD/RAB.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at V
WB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Different from operating current; supply current for NVM program lasts approximately 30 ms.
7 Different from operating current; supply current for NVM read lasts approximately 20 s.
8 P
DISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).
9 All dynamic characteristics use V
DD = 5.5 V, and VLOGIC = 5 V.
10 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C.
11 Retention lifetime equivalent at junction temperature (T
J) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
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