参数资料
型号: AD5162BRMZ2.5
厂商: Analog Devices Inc
文件页数: 8/20页
文件大小: 0K
描述: IC POT DUAL 2.5K 256POS 10-MSOP
标准包装: 50
接片: 256
电阻(欧姆): 2.5k
电路数: 2
温度系数: 标准值 35 ppm/°C
存储器类型: 易失
接口: 3 线串行(芯片选择)
电源电压: 2.7 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-MSOP
包装: 管件
产品目录页面: 786 (CN2011-ZH PDF)
配用: AD5162EVAL-ND - BOARD EVAL FOR AD5162
AD5162
Rev. C | Page 16 of 20
SPI INTERFACE
SPI-COMPATIBLE, 3-WIRE SERIAL BUS
The AD5162 contains a 3-wire, SPI-compatible digital interface
(SDI, CS, and CLK). The 9-bit serial word must be loaded MSB
first. The format of the word is shown in Table 8.
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
flip-flop or another suitable means. When CS is low, the clock
loads data into the serial register on each positive clock edge
The data setup and data hold times in Table 3 determine the
valid timing requirements. The AD5162 uses a 9-bit serial input
data register word that is transferred to the internal RDAC
register when the CS line returns to logic high. Extra MSB bits
are ignored.
Table 8. Serial Data-Word Format1
MSB
LSB
B8
B7
B6
B5
B4
B3
B2
B1
B0
A0
D7
D6
D5
D4
D3
D2
D1
D0
(28)
(27)
(20)
1 The values of bits are shown in parentheses.
SDI
CLK
CS
VOUT
RDAC REGISTER LOAD
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
04108-0-042
Figure 42. SPI Interface Timing Diagram
(VA = 5 V, VB = 0 V, VW = VOUT)
tCSH0
tCSS
tCL
tCH
tDS
tCSW
tS
tCS1
tCSH1
tCH
CLK
CS
VOUT
1
0
1
0
1
0
VDD
0
±1LSB
SDI
(DATA IN)
Dx
04
10
8-
0
-0
43
Figure 43. SPI Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT)
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