参数资料
| 型号： | AD5231BRUZ100-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/28页 |
| 文件大小： | 0K |
| 描述： | IC DGTL POT 100K 16-TSSOP |
| 标准包装： | 1,000 |
| 接片： | 1024 |
| 电阻（欧姆）： | 100k |
| 电路数： | 1 |
| 温度系数： | 标准值 600 ppm/°C |
| 存储器类型： | 非易失 |
| 接口： | 4 线 SPI（芯片选择） |
| 电源电压： | 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
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AD5231
Data Sheet
Rev. D | Page 16 of 28
TERMINAL VOLTAGE OPERATION RANGE
The AD5231’s positive VDD and negative VSS power supplies
define the boundary conditions for proper 3-terminal digital
potentiometer operation. Supply signals present on the A, B,
and W terminals that exceed VDD or VSS are clamped by the
internal forward-biased diodes (see Figure 40).
The ground pin of the AD5231 device is primarily used as a
digital ground reference, which needs to be tied to the common
ground of the PCB. The digital input control signals to the
AD5231 must be referenced to the device ground pin (GND)
and satisfy the logic level defined in the Specifications section.
An internal level-shift circuit ensures that the common-mode
voltage range of the three terminals extends from VSS to VDD,
regardless of the digital input level.
VSS
VDD
A
W
B
02739-
039
Figure 40. Maximum Terminal Voltages Set by VDD and VSS
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at the
A, B, and W terminals (Figure 40), it is important to power
VDD/VSS first before applying any voltage to Terminal A,
Terminal B, and Terminal W. Otherwise, the diode is forward-
biased such that VDD/VSS are powered unintentionally and
might affect the rest of the user’s circuit. The ideal power-up
sequence is GND, VDD, VSS, digital inputs, and VA/VB/VW. The
order of powering VA, VB, VW, and digital inputs is not
important as long as they are powered after VDD/VSS.
Regardless of the power-up sequence and the ramp rates of the
power supplies, once VDD/VSS are powered, the power-on preset
remains effective, which restores the EEMEM value to the
RDAC register.
LATCHED DIGITAL OUTPUTS
A pair of digital outputs, O1 and O2, is available on the
AD5231. These outputs provide a nonvolatile Logic 0 or Logic 1
setting. O1 and O2 are standard CMOS logic outputs, shown in
Figure 41. These outputs are ideal to replace the functions often
provided by DIP switches. In addition, they can be used to drive
other standard CMOS logic-controlled parts that need an
occasional setting change. Pin O1 and Pin O2 default to Logic 1,
and they can drive up to 50 mA of load at 5 V/25°C.
VDD
GND
OUTPUTS
O1 AND O2
PINS
02739-
040
Figure 41. Logic Outputs O1 and O2
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| AD5231BRUZ10-REEL7 | 功能描述:IC DGTL POT 1024POS 10K 16TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 接片:256 电阻（欧姆）:100k 电路数:1 温度系数:标准值 35 ppm/°C 存储器类型:非易失 接口:3 线串口 电源电压:2.7 V ~ 5.25 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WDFN 裸露焊盘 供应商设备封装:8-TDFN-EP（3x3） 包装:剪切带 (CT) 产品目录页面:1399 (CN2011-ZH PDF) 其它名称:MAX5423ETA+TCT |
| AD5231BRUZ50 | 功能描述:IC POT DGTL 1024POS 16-TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 接片:256 电阻（欧姆）:100k 电路数:1 温度系数:标准值 35 ppm/°C 存储器类型:非易失 接口:3 线串口 电源电压:2.7 V ~ 5.25 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WDFN 裸露焊盘 供应商设备封装:8-TDFN-EP（3x3） 包装:剪切带 (CT) 产品目录页面:1399 (CN2011-ZH PDF) 其它名称:MAX5423ETA+TCT |
| AD5231BRUZ50-REEL7 | 功能描述:IC POT DGTL 1024POS 16TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:- 标准包装:3,000 系列:DPP 接片:32 电阻（欧姆）:10k 电路数:1 温度系数:标准值 300 ppm/°C 存储器类型:非易失 接口:3 线串行（芯片选择，递增，增/减） 电源电压:2.5 V ~ 6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WFDFN 裸露焊盘 供应商设备封装:8-TDFN（2x3） 包装:带卷 (TR) |
| AD5232 | 制造商:AD 制造商全称:Analog Devices 功能描述:Nonvolatile Memory Digital Potentiometers |
| AD5232BRU10 | 功能描述:IC DGTL POT 256POS 10K 16TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:- 标准包装:3,300 系列:WiperLock™ 接片:257 电阻（欧姆）:100k 电路数:1 温度系数:标准值 150 ppm/°C 存储器类型:易失 接口:3 线 SPI（芯片选择） 电源电压:1.8 V ~ 5.5 V 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:8-VDFN 裸露焊盘 供应商设备封装:8-DFN-EP（3x3） 包装:带卷 (TR) |
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