AD5247
LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE
While most legacy systems may be operated at one voltage, a
new component may be optimized at another. When two
systems operate the same signal at two different voltages, proper
level shifting is needed. For instance, one can use a 3.3 V
E
2
PROM to interface with a 5 V digital potentiometer. A level
shifting scheme is needed to enable a bidirectional communi-
cation so that the setting of the digital potentiometer can be
stored to and retrieved from the E
2
PROM. F
of the implementations. M1 and M2 can be any N channel
signal FETs, or if V
DD
falls below 2.5 V, M1 and M2 can be low
threshold FETs such as the FDV301N.
A
V
DD
W
GND
0
shows one
igure 35
Figure 35. Level Shifting for Operation at Different Potentials
E
2
PROM
AD5247
SDA1
SCL1
D
G
R
P
R
P
3.3V
5V
S
M1
SCL2
SDA2
R
P
R
P
G
S
M2
V
DD1
= 3.3V
V
DD2=
5V
D
0
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in
This applies to the digital input pins SDA and SCL.
and
.
Figure 36
Figure 36. ESD Protection of Digital Pins
Figure 37
Figure 37. ESD Protection of Resistor Terminals
LOGIC
340
GND
0
A,W
0
GND
TERMINAL VOLTAGE OPERATING RANGE
The AD5247 V
DD
and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer
operation. Supply signals present on terminals A and W that
exceed V
DD
or GND will be clamped by the internal forward
biased diodes (see
).
Figure 38
Figure 38. Maximum Terminal Voltages Set by V
DD
and GND
igure 38
MAXIMUM OPERATING CURRENT
At low code values, the user should be aware that due to low
resistance values, the current through the RDAC may exceed
the 5 mA limit. In F
, a 5 V supply is placed on the wiper,
and the current through terminals W and B is plotted with
respect to code. A line is also drawn denoting the 5 mA current
limit. Note that at low code values (particularly for the 5 kΩ and
10 kΩ options), the current level increases significantly. Care
should be taken to limit the current flow between W and B in
this state to a maximum continuous current of 5 mA and a
maximum pulse current of no more than 20 mA. Otherwise,
degradation or possible destruction of the internal switch
contacts can occur.
igure 39
Figure 39. Maximum Operating Current
CODE (Decimal)
I
0
0.01
0.10
1.00
10.00
16
32
48
64
80
96
112
128
100.00
0
5mA CURRENT LIMIT
R
AB
= 5k
R
AB
= 10k
R
AB
= 100k
R
AB
= 50k
POWER-UP SEQUENCE
Since the ESD protection diodes limit the voltage compliance at
terminals A and W (see F
V
DD
/GND before applying any voltage to terminals A and W;
otherwise, the diode will be forward biased such that V
DD
will be
powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, V
DD
, digital inputs, and then V
A
/V
W
. The relative order of
powering V
A
and V
W
and the digital inputs is not important as
long as they are powered after V
DD
/GND.
), it is important to power
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